@Luka

i did some further routing , i am now at the power routing and constrain regions etc…

Most of the signals (only 2-4 traces missing i think) are done and the ethernet is fixed… now only power and other stuff and its done !!! :)

I did a bunch of routing , everything from usb (includes redoing the usb3.0 stuff) , hdmi and mipi dsi and some other small stuff and fixes , and i found out that i am missing some parts like resistors at the ethernet schematic …

So today i decidet because stardance ends this month i dont have time for all the planned ideas , the mainboard is now some small features poorer like mipi csi cam port and sd but maybe i will add it back… but i changed some power parts and other things on the board . This will be the rough layout , its matched to sepperate power sections from high speed signals like form the ram , while having priority on fast signals and pheripherntials further away … Now that i think of it i will propably add an small glue spacer under the oled so it doesnt mess up any signals … The Fpga will now be a SOM module so i can make a devboard in the future while still use it in the detector panel wich i will make after the mainboard and som … Also i know the layout and parts placement etc is messy but this is just the rough layout as I said…..

A final change to the emmc , may logs i know but i didnt want the emmc to break the rest of the system so this is the final rev i hope !

I totally forgot about a signal layer so i redone the full design !

I addet the emmc routing , this was weirdly harder than the ram , to match the impedance i couldnt go between the bga pins and also they were pretty mixed up so i redid it some times and now its good ! All the importand to match in length signals are matched by impedance and trace length / distance to other tracks and via count …

i finally routed the lpddr4 with its different impedances , differential pairs , via and lentgh matching . The power traces will come later …

After much time i finally figured out how the reference desing uses such tiny trace width for the ddr routing . They had to use such small trace width to route it between the bga pins but that would not be the needet 80-100ohm impedance on the noncopular differential pair . The trick was they used a different trace spacing to archive around 120ohm +- toleranze ! I also have redone some of the bottom caps for easy routing and no interferance problems !

Today i routed many of the caps wich need to be under the rockchip for power filtering , if to far away it would cause an to high path inductance … it was a little tricky to get them all in place and not to near to each other … some caps will be around it on the pmic and other power sources as the bulk caps do not need to be near the pins always !

This was a really long routing session , on the way i changed some part sizes , and had some fun time (absolute hell) playing tetris with the ram ic , where what cap goes under or on the side of the ram . same for all of the different routing parts , also I saw that this will need an 8 layer board …

I started to do the layout of the Rockchip board , on the picture you can see the rockchip pmic , the bottom and top layer design is carefully considered for thermal and noise reduction . Also i swapped some components like cap footprint sizes where possible !

I found out that i had many caps way to big to fit under the rockchip (bottom pcb side), its essential for some caps to be near the pins in power domains like low voltage or any sensitive soc stuff … then i changed the caps manually 🫠 . I made a green box around bottom caps and then made the CSI adapter (eg. for a cam) , I cleaned up some schematics in sepperate pages . I connected some headders for gipos and uart/i2c and made the final schematic fixes and changes …. now the routing wich as you can see will be hell ! I almost forgot to mention i addet an small 0.9” spi tft . As you can see the schematic looks more like a neural network or spiderweb than routing , but atleast its not as bad as the fpga will be in routing !

Sadly i found out the rockchip only supports pcie in host mode , to i cant really make a pcie card from it but its not the end of the world , i removed the 12v power mux system and then addet an oculink adapter , the oculink will also be on the fpga devboard but with more than the rockchip x1 pcie … then i connected some pins , while also having the problem of finding 2 suitable pins on a 3.3v bank near the pcie !

I connected many of the systems to the rockchip and did some datasheet reading to know how eg. the Pcie Interface is intendet to be made ont the Rockchip..

I finished the USB-C new Connector and then made the 2Port Usb 2.0 , after that i addet an Usb 3.0 Port and used the design rules/constrains by the hardware design guide from Rockchip

You know the best about lookout , its bugs … i mean it nicely captured the hdmi schematic , i used the reference design form a rk3566 board and swapped the connector and some power things . But when i got to USB , wich includet swapping the USB-c to a right angle one for the Pcie card to save space , and adding a usb 2.0 (2 port) . I saw it didnt capture because some screen minimizing error … but its not the end of the world , it was just choosing an suitable usb c and swapping it with the old one , using the datasheet to find out the function of some pin circuitry in the reference design , and doing some brainstorming , i will add a female usb 3.0 port because i dont need the sata interface on the phy ! Also i addet a uart debug port.. and the usb c otg and pwr screenshot is unfinished as i will procced with a fresh lookout recording

I finished the PWR MUX , when pcie is used then it gets the 12v and 3.3v , that means the usb 5 to 3.3v and the 5v from usb cant be on at the same time , this power mux design wich was a headache because of many states and sometimes wierd graphs passes the 5v from usb to system and the 3.3v buck (from usb 5v) output to the system normally . When 12v is detected it disconnects these power lanes and activates an 12v to 5v buck aswell as the 3.3v from pcie is used then !

This was funny and dumb enough to be a reason for a journal . I compared some parts for the load switch (mux type) and when i picked one and looked at the datasheet i was confused for a good amount of time , turns out i was looking at a datasheet for a similar part and that explained why some things totally didnt match !

I started by connecting the ethernet IC to the rockchip , after that i started brainstorming and testing around wich pcie or oculink or similar i would use for the interconnect of the devboards . I decidet to make the rockchip devboard onto an pcie card , it can work as pcie or standalone wich in the end started a hunt for an good 2 channel P mosfet , because if pcie is used it gives me 12v(step down to 5v) and 3.3v so the 5v from usb isnt needet aswell as the 5 to 3.3v so i have to switch it off when the 12v is applied but thats smth for tomorrow