@Luka

I totally forgot to add Testpoints haha , now there are some on the PWR rails !

My Last designing Devlog , its been a reallyyyyy long part of the project RadiaX but the FPGA SOM , aswell as the rockchip sbc are finished ! (wich is more of an placeholder rg , because the funding does not make it possible… ) I am happy to ship it NOW !

Long time no devlog but its just power routing and some tricky layout changes . The only sad part to switch from the kintex7 325T to a smaller variant , same for the ram …. funding 600$ cap :,)

I started by connecting the adapter , it worked first try , then i flashed some config to the eeprom with FT_PROG, afterwards I connected a second uart adapter and made a small serial blaster python file . Then python was missing and as i didnt want to fix the windows path hell i just reinstalled it and did some other work while that happend … Then i started going to my favorite(not) place (stackoverflow hell ) and did plan to make a auto discover wich gipos are wich com port , yeah i ran into some errors and stuff did a little AI help and after some coding the script works and I will now publish it to Github… Yeah the adapter works great !

The SOM was wayyy to expensive for the 600 dollar funding limit … so i had to choose an smaller LUTS fpga model and for it change the recommendet decoupling caps amount . Afterwards I changed some parts for cost saving and played around with coupons till it fit the 600 dollar funding limit … .. .

SO the devlog may seem long… but i lost 2 hours of footage while routing so yeah .. i routed the ddr3 , that includes the diff pairs , length matching and impedance constrains , etc … bla bla bla tech stuff , this took longer and was harder than the double stack (2 ics in one) lpddr4 on the rockchip board , idk why , propably placement and fpgas being tricky in general !

So marco made the Kintex Fpga a 3d model , there werent any good ones out there … Its the big metal thingy you can see in the middle of the Pcb . He send me the wrong footprint to installed freecad and resized it (I like fusion360 but i dont have it installed on my new laptop..) , Also I rendered the Pcb in blender ! I know the routing isnt finished but i really dont have the energie and time for it today !

I finished the Layout of the FPGA SOM , the filter caps have a really high footprint so that was tricky and the vtt resistors for the ddr3 , its a asingle ddr3 ic so that was weird …

The fpga SOM is now almost done , this was a faster pcb than i expected , i know it may look messy and crowdet but the pwr stuff is actually layouted in the best possible way(atleast i hope so) and some other things , now only some schematic finishing and checking is needet , then I can route and finish it !

THXXXX for the SUPER STAR !!!!! I finished the PWR filtering , i had to add some filter caps on the DDR3 . Then i used the LiteX Repo to see if i should add an EMMC , i decidet against it because of cost (already a problem…) and space constrains . But still i had to redo the Prog. section (mostly bank0 on the Kintex7) again because i accedently deleted it many journals ago when i sepperated the rockchip and kintex ! I went with a SPI flash (quad spi) … then I connected some mandatory config and other circuitry , this was mostly straightforward with the ref. designs and the ABSOLUTELY many documents on the AMD Technical Information Portal

The fpga SOM , PWR system is now finished . I already had the old power system but now its an smaller fpga package and power requirements , so i cleaned up suitable parts , let ai compare some dc/dc board mounts to safe space , designed some power sections and conmbined them all , etc…

I used the Mig Interface pin xdc file i created to connect the ddr3 to the fpga banks and then made the power interface for it !

I updates some parts , mostly cap placement because it was to crowdet and i made an export of the layers … https://github.com/Luka-io/RadiaX/blob/main/electronics/layers.pdf

After doing the rockchip sbc , i started with the fpga som , i will redo the power parts as i switched to a fpga (same model) with less pins , and a small package … i laso installed vivado wich totally hanged up my pc so i had to pause work , i needet to do it to get the pinout for the ddr3 to fpga (MIG = memory interface generator wizard) . The layout on the pic isnt the actual one , its just for testing , but the connector will stay like this ! Also i will now go back to the rockchip sbc for a short fixing !

I finally finished routing the board , some error hunting and silkscreen layout and its done !!! the 2 pwr layers are the turquoise and green

i did some further routing , i am now at the power routing and constrain regions etc…

Most of the signals (only 2-4 traces missing i think) are done and the ethernet is fixed… now only power and other stuff and its done !!! :)

I did a bunch of routing , everything from usb (includes redoing the usb3.0 stuff) , hdmi and mipi dsi and some other small stuff and fixes , and i found out that i am missing some parts like resistors at the ethernet schematic …

So today i decidet because stardance ends this month i dont have time for all the planned ideas , the mainboard is now some small features poorer like mipi csi cam port and sd but maybe i will add it back… but i changed some power parts and other things on the board . This will be the rough layout , its matched to sepperate power sections from high speed signals like form the ram , while having priority on fast signals and pheripherntials further away … Now that i think of it i will propably add an small glue spacer under the oled so it doesnt mess up any signals … The Fpga will now be a SOM module so i can make a devboard in the future while still use it in the detector panel wich i will make after the mainboard and som … Also i know the layout and parts placement etc is messy but this is just the rough layout as I said…..