@Luka

Today i finished hooking up the lpddr4(later x) to the rockchip soc , but while doing so and following the offical ref. design and datasheet i saw a problem they were talking about CS0A/B and CS1A/B ??? So i was totally confused as that are not valid lpddr4 pins as far as i know it , so i proccedet to look at other projects schematics and i saw some using it too , but when i looked up the offical ref design and thier Ram’s Datasheets i saw that these pins arent real there too (so if i am not wrong they all used the ref design wich was for a specific ram or smth because on all designs the pins are NC or DNU pins so defently not connect !) .. But before i didnt know that i thought my ram that i planned to use (lpddr4) only had this problem as the datasheet says 1CS pin but after switching to s stlightly bigger (lpddr4x) type Ram i saw its the same 1cs per bank so anyways now i have an new ram and buck converter on the board 🫠… I will defently include a deeper note on this in the Github Repo ! The Buck is on another schematic page (not on the screenshot) , but it is just a standart SY8089AAAC making the 0.6V , note that its importand to pick an stable and fast switching buck for precision parts (fast or precise) like ram

Small Journal , i did the hardware block diagramm of the Helios One board , it simplifies how the ARM-Soc and the FPGA are connected , thier power systems and pheripherentials…

Old journals from Macondo , i noticed that this is a standalone projekt and i started this Pcb (new revision / total change of schematic) after 1 July so it fits .. (summarized old journals with Ai !):

Summary of older Macondo journals because this project got moved over. The current revision of the board was started after 1 July and is a complete redesign around a Kintex7 FPGA and Rockchip SoC.

I started by researching how to program the FPGA and looked at supported JTAG solutions. After comparing datasheets, reference designs and available parts on LCSC I decided to use an FT2232H based solution because it supports both JTAG and UART and has good performance, although I might still switch to an external low cost programmer later.

One of the biggest architecture changes was switching from the original Rockchip choice to the RK3566. The larger Rockchip would have made routing on a 6 layer board extremely difficult and much more expensive. The RK3566 allows a cleaner and cheaper design while still supporting PCIe connectivity to the Kintex7 FPGA and MIPI DSI display output.

A large amount of time was spent designing the FPGA power system. I studied datasheets, reference designs and power sequencing requirements to determine which rails could share supplies and where tighter ripple and tolerance requirements were needed. Special attention was required for the FPGA MGT transceiver power rails used for high speed interfaces such as PCIe. Many reference designs relied on unavailable or very expensive parts so I selected alternatives and redesigned the sequencing around the LM3881 supervisor. During this process I also designed the DDR and DDRVTT supplies and completed the entire FPGA power architecture.

After finishing the FPGA side I moved on to the Rockchip power system. Using the datasheet and reference designs I adapted the design to remove unused functions while reusing parts already selected for the FPGA section to reduce BOM complexity and cost. I also had to replace an obsolete component with a software and hardware compatible alternative.

Another sidequest was selecting suitable LPDDR4 memory. After checking the Rockchip memory requirements and available parts I found a low cost memory IC with two x16 dies, allowing it to satisfy the required x32 memory interface while remaining compatible with the platform. The memory power requirements were already provided by the Rockchip PMIC so no additional regulators were needed.

Today I started placing the final filtering capacitors and connecting up the Rockchip section so that part is nearly finished. I also did some sidequests like determining pin requirements for the MIPI DSI display and Ethernet controller in preparation for the upcoming schematic work.

Old journals from Macondo , i noticed that this is a standalone projekt and i started this Pcb (new revision / total change of schematic) after 1 July so it fits .. (summarized old journals with Ai !):

Summary of older Macondo journals because this project got moved over. The current revision of the board was started after 1 July and is a complete redesign around a Kintex7 FPGA and Rockchip SoC.

I started by researching how to program the FPGA and looked at supported JTAG solutions. After comparing datasheets, reference designs and available parts on LCSC I decided to use an FT2232H based solution because it supports both JTAG and UART and has good performance, although I might still switch to an external low cost programmer later.

One of the biggest architecture changes was switching from the original Rockchip choice to the RK3566. The larger Rockchip would have made routing on a 6 layer board extremely difficult and much more expensive. The RK3566 allows a cleaner and cheaper design while still supporting PCIe connectivity to the Kintex7 FPGA and MIPI DSI display output.

A large amount of time was spent designing the FPGA power system. I studied datasheets, reference designs and power sequencing requirements to determine which rails could share supplies and where tighter ripple and tolerance requirements were needed. Special attention was required for the FPGA MGT transceiver power rails used for high speed interfaces such as PCIe. Many reference designs relied on unavailable or very expensive parts so I selected alternatives and redesigned the sequencing around the LM3881 supervisor. During this process I also designed the DDR and DDRVTT supplies and completed the entire FPGA power architecture.

After finishing the FPGA side I moved on to the Rockchip power system. Using the datasheet and reference designs I adapted the design to remove unused functions while reusing parts already selected for the FPGA section to reduce BOM complexity and cost. I also had to replace an obsolete component with a software and hardware compatible alternative.

Another sidequest was selecting suitable LPDDR4 memory. After checking the Rockchip memory requirements and available parts I found a low cost memory IC with two x16 dies, allowing it to satisfy the required x32 memory interface while remaining compatible with the platform. The memory power requirements were already provided by the Rockchip PMIC so no additional regulators were needed.

Today I started placing the final filtering capacitors and connecting up the Rockchip section so that part is nearly finished. I also did some sidequests like determining pin requirements for the MIPI DSI display and Ethernet controller in preparation for the upcoming schematic work.