Helios One

Usb Host , the Fpga needs an Jtag for programming and config + an uart for communication so i wanted to pick the mostly used FT2232H wich features 2 buses (for my case 1 jtag and 1 uart) . But then i thought while researching reference schematics , kintex7 and vivado compability and reading the datasheet , if i shouldnt just use an FT4232HL , but why that ? the rockchip also needs an uart for debug and i thought about adding a jtag but it turned out its internally , now the FT4232HL has 4 buses ’ 2 of them can do jtag and 2 uart (or other protocols btw) so i went with that and started designing it , took longer than expected as the eeprom selection and crystal isnt really troughout in the datasheet … so now i have an jtag and uart for the fpga , one for the rockchip debug and 1 additional port i will find a use for eventually … but the rockchip still needs an usb direct connection so it will get 2 usb c ports , a multiplexer isnt good here as it would prevent from using any fpga (or uart debug on rockchip) while doing otg (eg. flashing or other stuff ) .. Btw the screenshot is only a fraction of the schematic of it as stardance shows the boring part of the full screenshot so i cropped it

Finished Emmc Flash for Rockchip Soc , As the ddr4 is now finished i wanted to move on to the emmc flash , so i locked up the list of supported emmc parts but the list was from 2024 and had 2 model options for the RK3566 B/C but i had E??? So i was a little confused and began research but there was nothing so i scrapped the internet to find some newer list , eventually i found a updated one and there was a huge and i mean really huge list of tested emmc… I looked up wich ones are avaible on lcsc in my prefered GB size and picked one but after hooking up some connections i saw a problem , to use the H200 or H400 protocol speed like the rockchip wants VCCQ would need to be 1.8v but the datasheed meintion many times the chip can only work for 1 hour at a time then (also even finding the datasheet was hard) .. so i had to research and eventually found a better pick wich i hooked up and i changed the voltage config pins for the flash voltage on the rockchip addet some filters on the pwr lines and also hooked it up to the rockchip (not on the screenshot , other schem. page) .. there i addet the by the datasheet required parts and by the emmc datasheet …. also i addet a button to DAT0 , if this pin is connected to GND wich the button does when pressed the rockchip enters a failsafe mode .. this is a non brickable in soc safed mode that enables reflash/unbricking the soc over usb in case it happens (called Maskroom) …

Today i finished hooking up the lpddr4(later x) to the rockchip soc , but while doing so and following the offical ref. design and datasheet i saw a problem they were talking about CS0A/B and CS1A/B ??? So i was totally confused as that are not valid lpddr4 pins as far as i know it , so i proccedet to look at other projects schematics and i saw some using it too , but when i looked up the offical ref design and thier Ram’s Datasheets i saw that these pins arent real there too (so if i am not wrong they all used the ref design wich was for a specific ram or smth because on all designs the pins are NC or DNU pins so defently not connect !) .. But before i didnt know that i thought my ram that i planned to use (lpddr4) only had this problem as the datasheet says 1CS pin but after switching to s stlightly bigger (lpddr4x) type Ram i saw its the same 1cs per bank so anyways now i have an new ram and buck converter on the board 🫠… I will defently include a deeper note on this in the Github Repo ! The Buck is on another schematic page (not on the screenshot) , but it is just a standart SY8089AAAC making the 0.6V , note that its importand to pick an stable and fast switching buck for precision parts (fast or precise) like ram

Small Journal , i did the hardware block diagramm of the Helios One board , it simplifies how the ARM-Soc and the FPGA are connected , thier power systems and pheripherentials…

Old journals from Macondo , i noticed that this is a standalone projekt and i started this Pcb (new revision / total change of schematic) after 1 July so it fits .. (summarized old journals with Ai !):

Summary of older Macondo journals because this project got moved over. The current revision of the board was started after 1 July and is a complete redesign around a Kintex7 FPGA and Rockchip SoC.

I started by researching how to program the FPGA and looked at supported JTAG solutions. After comparing datasheets, reference designs and available parts on LCSC I decided to use an FT2232H based solution because it supports both JTAG and UART and has good performance, although I might still switch to an external low cost programmer later.

One of the biggest architecture changes was switching from the original Rockchip choice to the RK3566. The larger Rockchip would have made routing on a 6 layer board extremely difficult and much more expensive. The RK3566 allows a cleaner and cheaper design while still supporting PCIe connectivity to the Kintex7 FPGA and MIPI DSI display output.

A large amount of time was spent designing the FPGA power system. I studied datasheets, reference designs and power sequencing requirements to determine which rails could share supplies and where tighter ripple and tolerance requirements were needed. Special attention was required for the FPGA MGT transceiver power rails used for high speed interfaces such as PCIe. Many reference designs relied on unavailable or very expensive parts so I selected alternatives and redesigned the sequencing around the LM3881 supervisor. During this process I also designed the DDR and DDRVTT supplies and completed the entire FPGA power architecture.

After finishing the FPGA side I moved on to the Rockchip power system. Using the datasheet and reference designs I adapted the design to remove unused functions while reusing parts already selected for the FPGA section to reduce BOM complexity and cost. I also had to replace an obsolete component with a software and hardware compatible alternative.

Another sidequest was selecting suitable LPDDR4 memory. After checking the Rockchip memory requirements and available parts I found a low cost memory IC with two x16 dies, allowing it to satisfy the required x32 memory interface while remaining compatible with the platform. The memory power requirements were already provided by the Rockchip PMIC so no additional regulators were needed.

Today I started placing the final filtering capacitors and connecting up the Rockchip section so that part is nearly finished. I also did some sidequests like determining pin requirements for the MIPI DSI display and Ethernet controller in preparation for the upcoming schematic work.