Helios One

i did some further routing , i am now at the power routing and constrain regions etc…

Most of the signals (only 2-4 traces missing i think) are done and the ethernet is fixed… now only power and other stuff and its done !!! :)

I did a bunch of routing , everything from usb (includes redoing the usb3.0 stuff) , hdmi and mipi dsi and some other small stuff and fixes , and i found out that i am missing some parts like resistors at the ethernet schematic …

So today i decidet because stardance ends this month i dont have time for all the planned ideas , the mainboard is now some small features poorer like mipi csi cam port and sd but maybe i will add it back… but i changed some power parts and other things on the board . This will be the rough layout , its matched to sepperate power sections from high speed signals like form the ram , while having priority on fast signals and pheripherntials further away … Now that i think of it i will propably add an small glue spacer under the oled so it doesnt mess up any signals … The Fpga will now be a SOM module so i can make a devboard in the future while still use it in the detector panel wich i will make after the mainboard and som … Also i know the layout and parts placement etc is messy but this is just the rough layout as I said…..

A final change to the emmc , may logs i know but i didnt want the emmc to break the rest of the system so this is the final rev i hope !

I totally forgot about a signal layer so i redone the full design !

I addet the emmc routing , this was weirdly harder than the ram , to match the impedance i couldnt go between the bga pins and also they were pretty mixed up so i redid it some times and now its good ! All the importand to match in length signals are matched by impedance and trace length / distance to other tracks and via count …

i finally routed the lpddr4 with its different impedances , differential pairs , via and lentgh matching . The power traces will come later …

After much time i finally figured out how the reference desing uses such tiny trace width for the ddr routing . They had to use such small trace width to route it between the bga pins but that would not be the needet 80-100ohm impedance on the noncopular differential pair . The trick was they used a different trace spacing to archive around 120ohm +- toleranze ! I also have redone some of the bottom caps for easy routing and no interferance problems !

Today i routed many of the caps wich need to be under the rockchip for power filtering , if to far away it would cause an to high path inductance … it was a little tricky to get them all in place and not to near to each other … some caps will be around it on the pmic and other power sources as the bulk caps do not need to be near the pins always !

This was a really long routing session , on the way i changed some part sizes , and had some fun time (absolute hell) playing tetris with the ram ic , where what cap goes under or on the side of the ram . same for all of the different routing parts , also I saw that this will need an 8 layer board …

I started to do the layout of the Rockchip board , on the picture you can see the rockchip pmic , the bottom and top layer design is carefully considered for thermal and noise reduction . Also i swapped some components like cap footprint sizes where possible !

I found out that i had many caps way to big to fit under the rockchip (bottom pcb side), its essential for some caps to be near the pins in power domains like low voltage or any sensitive soc stuff … then i changed the caps manually 🫠 . I made a green box around bottom caps and then made the CSI adapter (eg. for a cam) , I cleaned up some schematics in sepperate pages . I connected some headders for gipos and uart/i2c and made the final schematic fixes and changes …. now the routing wich as you can see will be hell ! I almost forgot to mention i addet an small 0.9” spi tft . As you can see the schematic looks more like a neural network or spiderweb than routing , but atleast its not as bad as the fpga will be in routing !

Sadly i found out the rockchip only supports pcie in host mode , to i cant really make a pcie card from it but its not the end of the world , i removed the 12v power mux system and then addet an oculink adapter , the oculink will also be on the fpga devboard but with more than the rockchip x1 pcie … then i connected some pins , while also having the problem of finding 2 suitable pins on a 3.3v bank near the pcie !

I connected many of the systems to the rockchip and did some datasheet reading to know how eg. the Pcie Interface is intendet to be made ont the Rockchip..

I finished the USB-C new Connector and then made the 2Port Usb 2.0 , after that i addet an Usb 3.0 Port and used the design rules/constrains by the hardware design guide from Rockchip

You know the best about lookout , its bugs … i mean it nicely captured the hdmi schematic , i used the reference design form a rk3566 board and swapped the connector and some power things . But when i got to USB , wich includet swapping the USB-c to a right angle one for the Pcie card to save space , and adding a usb 2.0 (2 port) . I saw it didnt capture because some screen minimizing error … but its not the end of the world , it was just choosing an suitable usb c and swapping it with the old one , using the datasheet to find out the function of some pin circuitry in the reference design , and doing some brainstorming , i will add a female usb 3.0 port because i dont need the sata interface on the phy ! Also i addet a uart debug port.. and the usb c otg and pwr screenshot is unfinished as i will procced with a fresh lookout recording

I finished the PWR MUX , when pcie is used then it gets the 12v and 3.3v , that means the usb 5 to 3.3v and the 5v from usb cant be on at the same time , this power mux design wich was a headache because of many states and sometimes wierd graphs passes the 5v from usb to system and the 3.3v buck (from usb 5v) output to the system normally . When 12v is detected it disconnects these power lanes and activates an 12v to 5v buck aswell as the 3.3v from pcie is used then !

This was funny and dumb enough to be a reason for a journal . I compared some parts for the load switch (mux type) and when i picked one and looked at the datasheet i was confused for a good amount of time , turns out i was looking at a datasheet for a similar part and that explained why some things totally didnt match !

I started by connecting the ethernet IC to the rockchip , after that i started brainstorming and testing around wich pcie or oculink or similar i would use for the interconnect of the devboards . I decidet to make the rockchip devboard onto an pcie card , it can work as pcie or standalone wich in the end started a hunt for an good 2 channel P mosfet , because if pcie is used it gives me 12v(step down to 5v) and 3.3v so the 5v from usb isnt needet aswell as the 5 to 3.3v so i have to switch it off when the 12v is applied but thats smth for tomorrow

I made many modular sections of the devboard but still the actual connections to the rockchip were missing , i also had to rearange some pins , add buttons and testpoints and fix some wiring mistakes that came along the way!

It turned out for the Ethernet port i wont use the SDIO interface but MIIG , i used the RTL8211F-CG and a ethernet port with includet magnetics . This time there were no reference designs , and as i didnt want to go back and forth searching for the pins of this interface on the rockchip , I used AI to search for them and made a quick check if the Ai is telling false statements by manual checking !

I had to wait for this devlog , since lapse has a bug not seeing your hackatime projects , if you have the same problem just go to hackatime and paste your exact project name into the field and it will synch to it ! So i addet an micro sd slot and also started thinking about wifi , but as this rockchip mainboard will mostly be used in the ct scanner i will skip wifi and use ethernet instead , if you ask why not both ? Its because the sd card uses an SDIO bus and I only have 1 left avaible so its either ethernet or wifi or some unecessary option of both , in the ct scanner wifi would anyways be kinda unecessary !

After carefull consideration (rembering the zynq fpga series exist ..) I decidet to split the system onto 2 boards , a rockchp sbc and a kintex7 devboard like genysis2 from digilent but they can still work along over pcie thorugh octolink ! This time i removed the current sense ic , moved and changed hte rochip to a standalone board , while also changing its power input to usb-c . I addet the intendet to use 10.1 tft from lcsc with a connector for mipi-dsi and touch connector , luckily lcsc already has an reference schmetic for it so i dont have to map a connector and pins myself !

PWR Monitoring , today i thought its gonna be a fast finish but it totally wasnt .. i started chossing a current meter ic and there were many options eg. : hall effect but this isnt suitable for such a pcb , the routing and interference relally is not needet here , i originally planned to pick an current ic (1 channel with shunt circuit and i2c) but then i thought i have for the fpga part 4 rails i want to watch withouth interfereing with them , but the problem is that shunts at eg 1v20a full load would take to much W for my application from the bus … so i need small shunt values but some are too small for the ic to read and depending on ic have bad resolution .. So i picked for the 1v20a (most crutial rail) a 2.5mohm and for the rest a 5 ohm resistor .. Back to my solution , I went with a MICROCHIP PAC1934T-I/JQ (cheap , high stock and good specs , also has 4 channels wich is perfect !) , i hooked the circuit up after some datasheet and ref design reading and i am planning to maybe add another one to the board later for eg the usb of pcie pwr draw watching ! And also for the rockchip maybe but i will first have to check if the rockchips pmic already does it standalone ..

Today i didnt really have time for any big changes so i just started to add some Shunt resistor (and finding suitable values) matching for the INA219 . I did this so that i can monitor the pwr rails of the fpga while running for any problems … and i dont really have a screenshot to show , this is a special tiny journal on a busy day !

SODIMM DDR3 is now finished ! , so this was reallyyyyyy easy , there was a reference and good section about it in the Kintex7 Fpga design NOTE , i picked a SODIMM 204Pin ddr3 slot and connected it to the fpga banks , some resistors and caps were necessary for the jedec standart but why did i even bother to use sodimm ddr3 ? , so i could go with ddr4 but the kintex7 tool for memory implementation isnt really and neither the speed made for it , also i took sodimm as i am able to easily swap the ram to other sizes or vendors , the pcb routing is way easier and ram modules can also be cheaper often then the bare ic for ddr3 … and the most importand part there is a eeprom on the modules containing the timing constrains !!!

FPGA pwr Filter Caps selection… after the last journal i wanted to finally finish it so i went into the 7 Series FPGAs PCB Design Guide (UG483) , where cap values and count for the different FPGAs are listed , it went well other than searching for not in stock part alternatives (esr values are importand here and depending on cap listing there is no lcsc filter for it so i am going with good brands like murata and most popular filter and reading the datasheets till i find a fitting one ! ) … it defently wasnt so easy for the MGT pwr lines .. they are wayyyy more complicated and usecase depending ( https://docs.amd.com/v/u/en-US/ug476_7Series_Transceivers , or : https://docs.amd.com/v/u/en-US/ug471_7Series_SelectIO ) , but eventually i found a good middle between my needs and proven values from a ref. design . Lastly i addet the needet filter caps per FPGA bank and connected them up and thats it for this easy but redudant task !

Prog Page , so the schematic still needs sorting and all (not all off todays design is on the schem. page attached) … I finished the FT4232H circuit , then i started searching for a compatible flash from the PROG memory of the fpga , after pickcing one i made the circuit and proccedet to add a dip switch to select the fpga boot mode and connect the jtag from the FTDI ic … then i went over to make the USB-C circuit for the Rockchip and some of its filtering , afterwards i hocked up the FTDI to the debug port of the Rockchip . Lastly i addet the USB-C connector for the FTDI…

Usb Host , the Fpga needs an Jtag for programming and config + an uart for communication so i wanted to pick the mostly used FT2232H wich features 2 buses (for my case 1 jtag and 1 uart) . But then i thought while researching reference schematics , kintex7 and vivado compability and reading the datasheet , if i shouldnt just use an FT4232HL , but why that ? the rockchip also needs an uart for debug and i thought about adding a jtag but it turned out its internally , now the FT4232HL has 4 buses ’ 2 of them can do jtag and 2 uart (or other protocols btw) so i went with that and started designing it , took longer than expected as the eeprom selection and crystal isnt really troughout in the datasheet … so now i have an jtag and uart for the fpga , one for the rockchip debug and 1 additional port i will find a use for eventually … but the rockchip still needs an usb direct connection so it will get 2 usb c ports , a multiplexer isnt good here as it would prevent from using any fpga (or uart debug on rockchip) while doing otg (eg. flashing or other stuff ) .. Btw the screenshot is only a fraction of the schematic of it as stardance shows the boring part of the full screenshot so i cropped it

Finished Emmc Flash for Rockchip Soc , As the ddr4 is now finished i wanted to move on to the emmc flash , so i locked up the list of supported emmc parts but the list was from 2024 and had 2 model options for the RK3566 B/C but i had E??? So i was a little confused and began research but there was nothing so i scrapped the internet to find some newer list , eventually i found a updated one and there was a huge and i mean really huge list of tested emmc… I looked up wich ones are avaible on lcsc in my prefered GB size and picked one but after hooking up some connections i saw a problem , to use the H200 or H400 protocol speed like the rockchip wants VCCQ would need to be 1.8v but the datasheed meintion many times the chip can only work for 1 hour at a time then (also even finding the datasheet was hard) .. so i had to research and eventually found a better pick wich i hooked up and i changed the voltage config pins for the flash voltage on the rockchip addet some filters on the pwr lines and also hooked it up to the rockchip (not on the screenshot , other schem. page) .. there i addet the by the datasheet required parts and by the emmc datasheet …. also i addet a button to DAT0 , if this pin is connected to GND wich the button does when pressed the rockchip enters a failsafe mode .. this is a non brickable in soc safed mode that enables reflash/unbricking the soc over usb in case it happens (called Maskroom) …

Today i finished hooking up the lpddr4(later x) to the rockchip soc , but while doing so and following the offical ref. design and datasheet i saw a problem they were talking about CS0A/B and CS1A/B ??? So i was totally confused as that are not valid lpddr4 pins as far as i know it , so i proccedet to look at other projects schematics and i saw some using it too , but when i looked up the offical ref design and thier Ram’s Datasheets i saw that these pins arent real there too (so if i am not wrong they all used the ref design wich was for a specific ram or smth because on all designs the pins are NC or DNU pins so defently not connect !) .. But before i didnt know that i thought my ram that i planned to use (lpddr4) only had this problem as the datasheet says 1CS pin but after switching to s stlightly bigger (lpddr4x) type Ram i saw its the same 1cs per bank so anyways now i have an new ram and buck converter on the board 🫠… I will defently include a deeper note on this in the Github Repo ! The Buck is on another schematic page (not on the screenshot) , but it is just a standart SY8089AAAC making the 0.6V , note that its importand to pick an stable and fast switching buck for precision parts (fast or precise) like ram

Small Journal , i did the hardware block diagramm of the Helios One board , it simplifies how the ARM-Soc and the FPGA are connected , thier power systems and pheripherentials…

Old journals from Macondo , i noticed that this is a standalone projekt and i started this Pcb (new revision / total change of schematic) after 1 July so it fits .. (summarized old journals with Ai !):

Summary of older Macondo journals because this project got moved over. The current revision of the board was started after 1 July and is a complete redesign around a Kintex7 FPGA and Rockchip SoC.

I started by researching how to program the FPGA and looked at supported JTAG solutions. After comparing datasheets, reference designs and available parts on LCSC I decided to use an FT2232H based solution because it supports both JTAG and UART and has good performance, although I might still switch to an external low cost programmer later.

One of the biggest architecture changes was switching from the original Rockchip choice to the RK3566. The larger Rockchip would have made routing on a 6 layer board extremely difficult and much more expensive. The RK3566 allows a cleaner and cheaper design while still supporting PCIe connectivity to the Kintex7 FPGA and MIPI DSI display output.

A large amount of time was spent designing the FPGA power system. I studied datasheets, reference designs and power sequencing requirements to determine which rails could share supplies and where tighter ripple and tolerance requirements were needed. Special attention was required for the FPGA MGT transceiver power rails used for high speed interfaces such as PCIe. Many reference designs relied on unavailable or very expensive parts so I selected alternatives and redesigned the sequencing around the LM3881 supervisor. During this process I also designed the DDR and DDRVTT supplies and completed the entire FPGA power architecture.

After finishing the FPGA side I moved on to the Rockchip power system. Using the datasheet and reference designs I adapted the design to remove unused functions while reusing parts already selected for the FPGA section to reduce BOM complexity and cost. I also had to replace an obsolete component with a software and hardware compatible alternative.

Another sidequest was selecting suitable LPDDR4 memory. After checking the Rockchip memory requirements and available parts I found a low cost memory IC with two x16 dies, allowing it to satisfy the required x32 memory interface while remaining compatible with the platform. The memory power requirements were already provided by the Rockchip PMIC so no additional regulators were needed.

Today I started placing the final filtering capacitors and connecting up the Rockchip section so that part is nearly finished. I also did some sidequests like determining pin requirements for the MIPI DSI display and Ethernet controller in preparation for the upcoming schematic work.