@Luka on Helios One · about 1 month ago 1h 39m logged I finished the Layout of the FPGA SOM , the filter caps have a really high footprint so that was tricky and the vtt resistors for the ddr3 , its a asingle ddr3 ic so that was weird …
@Luka on Helios One · about 1 month ago 1h 39m logged I finished the Layout of the FPGA SOM , the filter caps have a really high footprint so that was tricky and the vtt resistors for the ddr3 , its a asingle ddr3 ic so that was weird …
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