RISC-V SoC
By
@njfdev
- 1 Devlogs
- 4 Total hours
Full RISC-V system from scratch in System Verilog.
3h 46m 47s logged
I’ve set up a basic outline for my SOC project! I have a verilog project (an HDL for describing the CPU design) and a simultaneous operating system I am programming, called “nos”!
It is all done for the RISC-V ISA, and I have gotten basic printf functionality working in a qemu riscv32 emulator!
