RISC-V SoC
- 2 Devlogs
- 13 Total hours
Full RISC-V system from scratch in System Verilog.
Started getting my RISC-V CPU actually working in Verilog. So far I have implemented ADD, ADDI, and JAL, which have allowed to make a small program performing 18 + (3 + 6) and storing it in register x4 (which is correctly 27)!!
I’ve set up a basic outline for my SOC project! I have a verilog project (an HDL for describing the CPU design) and a simultaneous operating system I am programming, called “nos”!
It is all done for the RISC-V ISA, and I have gotten basic printf functionality working in a qemu riscv32 emulator!
