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RISC-V 32bit CPU

By @captaintriton10

  • 5 Devlogs
  • 15 Total hours

A simple RV32I CPU implementation with video output, for use on the icepi-zero FPGA board.
Ship #1 Pending review

@captaintriton10 on RISC-V 32bit CPU

This was my second attempt at making a working RISC-V CPU, I'm really happy with where the project is currently. The most difficult part so far has been trying to debug it when it isn't working, but I've managed to get assembly to run on it with video output, and also keyboard input. Next, I think I want to work on adding more extensions to the base ISA and writing more complex programs for it.

  • 5 devlogs
  • 15h
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@captaintriton10 on RISC-V 32bit CPU

1h 36m 38s logged

Worked some more on other typical features of a VGA text mode, such as highlighted text and blinking.

@captaintriton10

Worked some more on other typical features of a VGA text mode, such as highlighted text and blinking.

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@captaintriton10 on RISC-V 32bit CPU

5h 10m 41s logged

As you can see below, I got keyboard input to work, so now I can write programs that use keyboard input.

New features:

  • Character colours
  • UART input (keyboard input)

It’s pretty cool that I can also write the devlog on the CPU with the custom assembly code I wrote!

@captaintriton10

As you can see below, I got keyboard input to work, so now I can write programs that use keyboard input.

New features:

  • Character colours
  • UART input (keyboard input)

It’s pretty cool that I can also write the devlog on the CPU with the custom assembly code I wrote!

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@captaintriton10 on RISC-V 32bit CPU

1h 34m 45s logged

I finally fixed the branch logic, and proved that it works with this simple counter that uses the conditional BGE (branch if greater than or equal) instruction.

@captaintriton10

I finally fixed the branch logic, and proved that it works with this simple counter that uses the conditional BGE (branch if greater than or equal) instruction.

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@captaintriton10 on RISC-V 32bit CPU

4h 19m 52s logged

Currently working on debugging conditional branch instructions, as the wrong branch address is being targetted. Fortunately, I managed to fix the JAL and JALR jump instructions.

@captaintriton10

Currently working on debugging conditional branch instructions, as the wrong branch address is being targetted. Fortunately, I managed to fix the JAL and JALR jump instructions.

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@captaintriton10 on RISC-V 32bit CPU

2h 26m 13s logged

This is a project I’ve been working on already a fair bit, trying to make a half-decent RISC-V CPU for use on the icepi-zero FPGA board (that I got from the previous Flavourtown event :D). This is a testbench I’m running, currently trying to debug jump and branch instructions not working. My next step is adding keyboard input through the UART protocol (universal asynchronous receiver-transmitter)

@captaintriton10

This is a project I’ve been working on already a fair bit, trying to make a half-decent RISC-V CPU for use on the icepi-zero FPGA board (that I got from the previous Flavourtown event :D). This is a testbench I’m running, currently trying to debug jump and branch instructions not working. My next step is adding keyboard input through the UART protocol (universal asynchronous receiver-transmitter)

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