Completed Day 6 and 7 with finishing off the clock module and the register then I started on the RAM/MAR. I spent the last few days mapping out the core timing and memory architecture for the SAP-X. I started by designing a dual-mode system clock, deriving a hardware SR-latch from cross-coupled NAND gates to perfectly debounce the manual step button so it safely multiplexes with the astable clock signal. From there, I built a modular 8-bit register template using D-flip-flops paired with 74HCT245 tri-state buffers to guarantee bus isolation. After locking down the template, I instantiated four of these (Registers A, B, C, and the hidden TMP register) into the main master file, routed them to a shared 8-bit data bus, and ran stress tests to verify synchronous data latching while actively proving the tri-state buffers successfully prevent bus collision short-circuits. Nothing has been pushed to the github yet, since I haven’t completed anything 100%.

Sorry for the inactivity on the project, I had to deal with something else, but now I’m back!

Day 6 Lapse: https://lapse.hackclub.com/timelapse/h4tYPiUg90ZF
Day 7 Lapse: https://lapse.hackclub.com/timelapse/KAYLJKoEq5V8