SAP-X CPU

Completed Day 6 and 7 with finishing off the clock module and the register then I started on the RAM/MAR. I spent the last few days mapping out the core timing and memory architecture for the SAP-X. I started by designing a dual-mode system clock, deriving a hardware SR-latch from cross-coupled NAND gates to perfectly debounce the manual step button so it safely multiplexes with the astable clock signal. From there, I built a modular 8-bit register template using D-flip-flops paired with 74HCT245 tri-state buffers to guarantee bus isolation. After locking down the template, I instantiated four of these (Registers A, B, C, and the hidden TMP register) into the main master file, routed them to a shared 8-bit data bus, and ran stress tests to verify synchronous data latching while actively proving the tri-state buffers successfully prevent bus collision short-circuits. Nothing has been pushed to the github yet, since I haven’t completed anything 100%.

Sorry for the inactivity on the project, I had to deal with something else, but now I’m back!

Day 6 Lapse: https://lapse.hackclub.com/timelapse/h4tYPiUg90ZF
Day 7 Lapse: https://lapse.hackclub.com/timelapse/KAYLJKoEq5V8

Completed Day 5 by finishing off the ALU circuit. Added the other required components such as the SHR (one of the crucial input to the multiplexer and also has an op-code), and the ZERO_OUT and NEG_OUT flags, which flag if the CPU reads a 00000000 (ZERO_OUT), and when the most significant bit is a 1 which signifies a negative number (NEG_OUT), these flags are required to tell the computer about zeros and negatives when they are loaded onto the bus. Also, these 2 flags will be a part of the Flags Register later on.
Basically, today I just used splitter to get 1 bit outputs from 8 bits and used them to create the flags I described earlier. And I used logic to create the SHR which was also clever wiring of the splitter (SHR means the number’s bits are shifted right one place).
I will continue with the more important modules such as clock module in Day 6.

Today (Day 4), I added other operations to the ALU math, which was AND, OR, XOR, and NOT along with the addition and subtraction circuit that I created in Day 3. Moreover, I cleaned up the circuit schematic by using tunnels and splitters rather than messy wires stretching along the canvas.
Then, I used a multiplexer to feed in the different operation (AND, OR, XOR, NOT, ADD/SUB) as inputs and used a 3-bit selector input to select the operation that was to be executed. I tested the circuit, and it worked perfectly.
Now, the only things remaining are to implement SHL and SHR for the ALU.
Lapse recording: https://lapse.hackclub.com/timelapse/qAFKFWqHWpiz

To start off Day 3, I worked on the ALU (Arithmetic Logic Unit) of the CPU, which will perform addition and subtraction. I built the 8-bit adder/subtractor using 8-bit inputs for the first number to be added/subtracted: A0-A7 and the second number: B0-B7. Then, I used 2 full adder ICs and connected them in a ripple form, so that the C_out of the first one is the C_in to the second.
Then, I wired the logic that I implemented earlier, and tested a few combinations such as (5+3 = 8, 5-3=2, and etc.)
Here is the Lapse for Day 3 Part 1: https://lapse.hackclub.com/timelapse/HgUVg1cJHHOm

To start off Day 2, I started with creating the half and full adder circuits, which will be fundamental building blocks for the Arithmetic Logic Unit (ALU) of the CPU. These circuits help create the operations that were described in the ISA such as ADD rr and SUB rr (addition and subtraction using 8-bits)
Later, I will continue using these circuits to make a 8 bit calculator with the addition and subtraction operations after I am done researching how to efficiently do so.
Lapse Recording: https://lapse.hackclub.com/timelapse/GU3NyWpgJQYZ

Completed the block diagram as the second part of Day 1, completing the first day. The block diagram is not very detailed as something one can find in a computer engineering documentation, but is enough to indicate the various inputs and outputs from the central 8-bit bus to various components. This will help me very much during the IRL build of the project!
The Lapse for creating this: https://lapse.hackclub.com/timelapse/nQTostsh-AKQ

For the first day of this project, I went through the basics such as creating the GitHub repository and writing the Instruction Set Architecture (ISA), which maps readable text to binary numbers so that it passes commands to the CPU to do some function.

For example, when I write a program using the “mnemonics” such as “ADD B”, that is readable by a human being but not by a computer. The computer can only react to electrical voltages (1 = High, 0 = Low). The ISA is the specification that states “The text command ADD B is assigned the sequence 00101”.

When the CPU’s instruction register (IR) receives the voltage sequence 00101 from memory, the microcode (later to be implemented) interprets that sequence as a sequence of specific voltages and activates the exact logic required to route Register B into ALU addition, or in other words, route ADD B.

The Lapse of me implementing the ISA:
https://lapse.hackclub.com/timelapse/8zTdg_xyP0AZ