Six Boards Done, a Real Frame, and a Display Vendor Discovery

Big stretch since the last log: the program crossed from designing into spending mode, the frame became real CAD, and we found a vendor that might cut the biggest cost line in half.

What got done

• All six PCBs are fab-pack complete. Three bench boards (core, front, aux) and three in-frame prototype boards (p-core, p-front, p-aux), each with schematics, routed layout, gerbers, LCSC BOM, and pick and place files ready for JLCPCB. The hardest, p-core, carries a bare RK3566 with hand-routed LPDDR4 on 6-layer HDI.
• A full cost model with live pricing. One complete set of everything lands between $1,143 and $1,972, and the display engine alone is 44 to 51 percent of that.
• A 70-check verification pass: 50 clean, 15 documented exceptions, 5 real problems caught and fixed same day. Plus a 16-page Program Review PDF built from a script.
• Frame CAD v1, written as parametric code (build123d): seven printable pieces, split-half temples with a screwless post-in-socket board capture, my ear hook as one tangent chain, print-ready STL and STEP exports.

What we found

Verification is not paperwork, it keeps catching real things:

• The chirality catch. Seating the real p-core model in the real temple cavity showed the layout mirrored the wrong way, breaching the inner wall. The old box-based fit check could never see this. Caught before fab, so the fix is free.
• The 57.9 mm front. CAD proved the drawn 42 mm front cannot hold the old front board channel with legal walls. That forced a better architecture: camera flex straight to the main temple board (like shipped products), front board replaced by one thin sensor strip. Slimmer front, fewer connectors.
• Hongshi. A Chinese MicroLED maker building mono green microdisplays: 0.08 and 0.12 inch, 640x480, up to 8 million nits, SPI/QSPI native so zero changes to my boards, plus a matched engine + waveguide module that could collapse my two riskiest cost lines into one part. One of only two mass-production mono-green makers (the other is JBD). RFQ sent in English and Chinese.
• Samsung entered the category the same week: camera plus Gemini, no display, phone-tethered. Exactly the gap Luxera plays in: standalone Linux, an actual HUD, Arabic first.
• My prescription became a spec. I traced my real lenses (52□18-140, R.E. -2.00, L.E. -1.00, IPD 64.0) so the next frame is built around actual lens outlines. Bonus: the IPD is the display alignment target, since a monocular eyebox must center on the pupil, about 3 mm nasal of the lens center.

What is next

• The big rebuild: p-sense strip, p-core respin (mirror fix plus new connectors), and the frame regenerated around my real lens shapes with an anatomical nose bridge and hinge knuckles fused so every part prints as one watertight solid.
• MSLA print the right temple and wear-test the hook. Live JLCPCB quotes (quote only). Hongshi quote lands, then the engine decision vs JBD. Then the manager showcase.

The workflow, honestly

Claude Code is the engineering copilot: it writes the KiCad files and the CAD as code and runs for hours. I direct, review, catch the design smells, and make the calls. Nothing counts on vibes: every board answers to real ERC and DRC, every frame part to watertight, wall thickness, and collision checks. Longest single run: 2 days 15 hours.

Attached images

1. assembly-iso.png: frame CAD v1, full assembly
2. assembly-split-open.png: temples split open with the real boards seated inside
3. p-core-bottom.png: the prototype brain, bare RK3566 HDI board
4. p-front-iso.png: the front board that the new architecture retires

More soon: a printed temple, real quotes, and hopefully a display engine with a price tag.

Six Boards Done, a Real Frame, and a Display Vendor Discovery

Big stretch since the last log: the program crossed from designing into spending mode, the frame became real CAD, and we found a vendor that might cut the biggest cost line in half.

What got done

• All six PCBs are fab-pack complete. Three bench boards (core, front, aux) and three in-frame prototype boards (p-core, p-front, p-aux), each with schematics, routed layout, gerbers, LCSC BOM, and pick and place files ready for JLCPCB. The hardest, p-core, carries a bare RK3566 with hand-routed LPDDR4 on 6-layer HDI.
• A full cost model with live pricing. One complete set of everything lands between $1,143 and $1,972, and the display engine alone is 44 to 51 percent of that.
• A 70-check verification pass: 50 clean, 15 documented exceptions, 5 real problems caught and fixed same day. Plus a 16-page Program Review PDF built from a script.
• Frame CAD v1, written as parametric code (build123d): seven printable pieces, split-half temples with a screwless post-in-socket board capture, my ear hook as one tangent chain, print-ready STL and STEP exports.

What we found

Verification is not paperwork, it keeps catching real things:

• The chirality catch. Seating the real p-core model in the real temple cavity showed the layout mirrored the wrong way, breaching the inner wall. The old box-based fit check could never see this. Caught before fab, so the fix is free.
• The 57.9 mm front. CAD proved the drawn 42 mm front cannot hold the old front board channel with legal walls. That forced a better architecture: camera flex straight to the main temple board (like shipped products), front board replaced by one thin sensor strip. Slimmer front, fewer connectors.
• Hongshi. A Chinese MicroLED maker building mono green microdisplays: 0.08 and 0.12 inch, 640x480, up to 8 million nits, SPI/QSPI native so zero changes to my boards, plus a matched engine + waveguide module that could collapse my two riskiest cost lines into one part. One of only two mass-production mono-green makers (the other is JBD). RFQ sent in English and Chinese.
• Samsung entered the category the same week: camera plus Gemini, no display, phone-tethered. Exactly the gap Luxera plays in: standalone Linux, an actual HUD, Arabic first.
• My prescription became a spec. I traced my real lenses (52□18-140, R.E. -2.00, L.E. -1.00, IPD 64.0) so the next frame is built around actual lens outlines. Bonus: the IPD is the display alignment target, since a monocular eyebox must center on the pupil, about 3 mm nasal of the lens center.

What is next

• The big rebuild: p-sense strip, p-core respin (mirror fix plus new connectors), and the frame regenerated around my real lens shapes with an anatomical nose bridge and hinge knuckles fused so every part prints as one watertight solid.
• MSLA print the right temple and wear-test the hook. Live JLCPCB quotes (quote only). Hongshi quote lands, then the engine decision vs JBD. Then the manager showcase.

The workflow, honestly

Claude Code is the engineering copilot: it writes the KiCad files and the CAD as code and runs for hours. I direct, review, catch the design smells, and make the calls. Nothing counts on vibes: every board answers to real ERC and DRC, every frame part to watertight, wall thickness, and collision checks. Longest single run: 2 days 15 hours.

Attached images

1. assembly-iso.png: frame CAD v1, full assembly
2. assembly-split-open.png: temples split open with the real boards seated inside
3. p-core-bottom.png: the prototype brain, bare RK3566 HDI board
4. p-front-iso.png: the front board that the new architecture retires

More soon: a printed temple, real quotes, and hopefully a display engine with a price tag.

All 3 bench boards DONE (DRC zero) + a compute plot twist 🤯

Since last devlog the project went from “one schematic” to the entire bench board set finished and fab-ready — and one massive architecture correction.

Bench set — done ✅

• Core board routed from 149 unrouted nets → DRC ZERO (0 unconnected, 0 violations). Full JLCPCB fab pack: gerbers, BOM with LCSC part numbers, pick-and-place, assembly drawing.
• Front board (the 75mm rim board): camera FFC + VL53L8CX ToF + 2 PDM mics + voice-pickup sensor. Schematic ERC 0 → routed DRC 0 → fab pack.
• Aux board: nRF52832 BLE + BMI270/BMM150 IMU + bone-conduction audio. Same treatment, same result.

The routing war ⚔️

My custom A* autorouter got each board ~90% routed then hit a wall for days — escape congestion on 0.4mm-pitch connectors that greedy routing can’t solve. Fix: a fully headless pipeline —

KiCad Python API → Specctra DSN → Freerouting (real rip-up-and-reroute) → session import → kicad-cli DRC as the referee

The CSI fanout that blocked me for days fell in 28 seconds. Humbling.

The plot twist 🤯

The plan was a Radxa Zero 3W as the in-frame compute. Deep-dive before committing: it’s HDMI-only. No MIPI-DSI, no QSPI — it physically cannot drive the MicroLED display that the entire product exists for. Also it’s a 65×30mm brick that would never fit a glasses temple.

Killed it. Re-read the build guide cover to cover — the real design was always the bare RK3566 SoC soldered directly onto the temple board, with 2× LPDDR4 + eMMC + Rockchip’s RK817 PMIC around it.

So the real in-frame boards are now underway:

• Built the 565-ball, 0.4mm-pitch RK3566 BGA library part + LPDDR4 + eMMC + RK817 footprints — every ball count and pitch hand-verified against datasheets
• All three in-frame schematics at ERC 0 — the compute board alone is 171 parts, 508 nets, 1,396 pin connections wiring the bare SoC to everything
• Display path confirmed: RK3566 QSPI → JBD 0.13” green MicroLED engine — that’s how Vuzix/Rokid actually drive these engines, not DSI

Hard-won lessons 🔥

• Check the display bus before falling in love with a compute module. “Right SoC” ≠ “the pins you need are exposed.”
• Don’t rebuild mature tools: 8 sessions tuning a custom router lost to one afternoon of wiring Freerouting in headlessly.
• kicad-cli DRC re-reports exclusions the GUI accepts — document every waiver or your CI numbers lie.
• Imported BGA footprints are guilty until proven innocent — the PMIC footprint shipped with paste over its thermal vias (solder-wicking defect) and had to be reworked.

Next: layout + routing of the in-frame boards. The compute board is 6-layer HDI with DDR length-matching — that one gets a professional design review before any fab money. Then fab packs and the full branded bring-up & testing guide. 🔧

All 3 bench boards DONE (DRC zero) + a compute plot twist 🤯

Since last devlog the project went from “one schematic” to the entire bench board set finished and fab-ready — and one massive architecture correction.

Bench set — done ✅

• Core board routed from 149 unrouted nets → DRC ZERO (0 unconnected, 0 violations). Full JLCPCB fab pack: gerbers, BOM with LCSC part numbers, pick-and-place, assembly drawing.
• Front board (the 75mm rim board): camera FFC + VL53L8CX ToF + 2 PDM mics + voice-pickup sensor. Schematic ERC 0 → routed DRC 0 → fab pack.
• Aux board: nRF52832 BLE + BMI270/BMM150 IMU + bone-conduction audio. Same treatment, same result.

The routing war ⚔️

My custom A* autorouter got each board ~90% routed then hit a wall for days — escape congestion on 0.4mm-pitch connectors that greedy routing can’t solve. Fix: a fully headless pipeline —

KiCad Python API → Specctra DSN → Freerouting (real rip-up-and-reroute) → session import → kicad-cli DRC as the referee

The CSI fanout that blocked me for days fell in 28 seconds. Humbling.

The plot twist 🤯

The plan was a Radxa Zero 3W as the in-frame compute. Deep-dive before committing: it’s HDMI-only. No MIPI-DSI, no QSPI — it physically cannot drive the MicroLED display that the entire product exists for. Also it’s a 65×30mm brick that would never fit a glasses temple.

Killed it. Re-read the build guide cover to cover — the real design was always the bare RK3566 SoC soldered directly onto the temple board, with 2× LPDDR4 + eMMC + Rockchip’s RK817 PMIC around it.

So the real in-frame boards are now underway:

• Built the 565-ball, 0.4mm-pitch RK3566 BGA library part + LPDDR4 + eMMC + RK817 footprints — every ball count and pitch hand-verified against datasheets
• All three in-frame schematics at ERC 0 — the compute board alone is 171 parts, 508 nets, 1,396 pin connections wiring the bare SoC to everything
• Display path confirmed: RK3566 QSPI → JBD 0.13” green MicroLED engine — that’s how Vuzix/Rokid actually drive these engines, not DSI

Hard-won lessons 🔥

• Check the display bus before falling in love with a compute module. “Right SoC” ≠ “the pins you need are exposed.”
• Don’t rebuild mature tools: 8 sessions tuning a custom router lost to one afternoon of wiring Freerouting in headlessly.
• kicad-cli DRC re-reports exclusions the GUI accepts — document every waiver or your CI numbers lie.
• Imported BGA footprints are guilty until proven innocent — the PMIC footprint shipped with paste over its thermal vias (solder-wicking defect) and had to be reworked.

Next: layout + routing of the in-frame boards. The compute board is 6-layer HDI with DDR length-matching — that one gets a professional design review before any fab money. Then fab packs and the full branded bring-up & testing guide. 🔧

Core board schematic — DONE ✅

Finished the complete KiCad schematic for Luxera’s Core bench board (the “brain” board that the glasses’ electronics get proven on before shrinking into the frame).

What’s in it:

• Full battery power chain: USB-C in → MCP73831 charger → 2 parallel Li-ion cells → MAX17048 fuel gauge
• Three regulated rails: 3.3V buck (TPS62840), 1.8V LDO, and a 5V boost (TPS61023) for the compute module
• Socket for the RK3566 compute module (CM4-compatible, 2× 100-pin DF40 connectors, ~60 pins wired: power, USB, I²C, UART console, boot control)
• Two MAX98357A I²S amps for bone-conduction audio (left + right channels via SD_MODE resistor trick)
• Capacitive touch controller (IQS227B) + multifunction button
• Camera (2-lane MIPI CSI) + display (2-lane DSI) lanes broken out, and a 40-pin FFC that will link to the sensor board in the glasses’ front frame

Hard-won lessons today:

• Learned the difference between buck and boost topology the practical way — the inductor goes before SW on a boost, not after 😅
• ERC threw 140+ “errors” that were all one thing: the LCSC import tool doesn’t set pin types. Learned to read the report instead of panicking — it actually became a free wiring audit
• Caught a real bug in review: my camera I²C clock label had landed on pin 90 (a 1.8V power output!) instead of pin 80. Hover-checking pins is now religion

Next: footprint assignment, then the actual PCB layout — 4-layer board, 55×45mm.

Every part verified in stock at JLCPCB/LCSC. Repo committed. 🔧

Core board schematic — DONE ✅

Finished the complete KiCad schematic for Luxera’s Core bench board (the “brain” board that the glasses’ electronics get proven on before shrinking into the frame).

What’s in it:

• Full battery power chain: USB-C in → MCP73831 charger → 2 parallel Li-ion cells → MAX17048 fuel gauge
• Three regulated rails: 3.3V buck (TPS62840), 1.8V LDO, and a 5V boost (TPS61023) for the compute module
• Socket for the RK3566 compute module (CM4-compatible, 2× 100-pin DF40 connectors, ~60 pins wired: power, USB, I²C, UART console, boot control)
• Two MAX98357A I²S amps for bone-conduction audio (left + right channels via SD_MODE resistor trick)
• Capacitive touch controller (IQS227B) + multifunction button
• Camera (2-lane MIPI CSI) + display (2-lane DSI) lanes broken out, and a 40-pin FFC that will link to the sensor board in the glasses’ front frame

Hard-won lessons today:

• Learned the difference between buck and boost topology the practical way — the inductor goes before SW on a boost, not after 😅
• ERC threw 140+ “errors” that were all one thing: the LCSC import tool doesn’t set pin types. Learned to read the report instead of panicking — it actually became a free wiring audit
• Caught a real bug in review: my camera I²C clock label had landed on pin 90 (a 1.8V power output!) instead of pin 80. Hover-checking pins is now religion

Next: footprint assignment, then the actual PCB layout — 4-layer board, 55×45mm.

Every part verified in stock at JLCPCB/LCSC. Repo committed. 🔧