All 3 bench boards DONE (DRC zero) + a compute plot twist 🤯

Since last devlog the project went from “one schematic” to the entire bench board set finished and fab-ready — and one massive architecture correction.

Bench set — done ✅

• Core board routed from 149 unrouted nets → DRC ZERO (0 unconnected, 0 violations). Full JLCPCB fab pack: gerbers, BOM with LCSC part numbers, pick-and-place, assembly drawing.
• Front board (the 75mm rim board): camera FFC + VL53L8CX ToF + 2 PDM mics + voice-pickup sensor. Schematic ERC 0 → routed DRC 0 → fab pack.
• Aux board: nRF52832 BLE + BMI270/BMM150 IMU + bone-conduction audio. Same treatment, same result.

The routing war ⚔️

My custom A* autorouter got each board ~90% routed then hit a wall for days — escape congestion on 0.4mm-pitch connectors that greedy routing can’t solve. Fix: a fully headless pipeline —

KiCad Python API → Specctra DSN → Freerouting (real rip-up-and-reroute) → session import → kicad-cli DRC as the referee

The CSI fanout that blocked me for days fell in 28 seconds. Humbling.

The plot twist 🤯

The plan was a Radxa Zero 3W as the in-frame compute. Deep-dive before committing: it’s HDMI-only. No MIPI-DSI, no QSPI — it physically cannot drive the MicroLED display that the entire product exists for. Also it’s a 65×30mm brick that would never fit a glasses temple.

Killed it. Re-read the build guide cover to cover — the real design was always the bare RK3566 SoC soldered directly onto the temple board, with 2× LPDDR4 + eMMC + Rockchip’s RK817 PMIC around it.

So the real in-frame boards are now underway:

• Built the 565-ball, 0.4mm-pitch RK3566 BGA library part + LPDDR4 + eMMC + RK817 footprints — every ball count and pitch hand-verified against datasheets
• All three in-frame schematics at ERC 0 — the compute board alone is 171 parts, 508 nets, 1,396 pin connections wiring the bare SoC to everything
• Display path confirmed: RK3566 QSPI → JBD 0.13” green MicroLED engine — that’s how Vuzix/Rokid actually drive these engines, not DSI

Hard-won lessons 🔥

• Check the display bus before falling in love with a compute module. “Right SoC” ≠ “the pins you need are exposed.”
• Don’t rebuild mature tools: 8 sessions tuning a custom router lost to one afternoon of wiring Freerouting in headlessly.
• kicad-cli DRC re-reports exclusions the GUI accepts — document every waiver or your CI numbers lie.
• Imported BGA footprints are guilty until proven innocent — the PMIC footprint shipped with paste over its thermal vias (solder-wicking defect) and had to be reworked.

Next: layout + routing of the in-frame boards. The compute board is 6-layer HDI with DDR length-matching — that one gets a professional design review before any fab money. Then fab packs and the full branded bring-up & testing guide. 🔧

Core board schematic — DONE ✅

Finished the complete KiCad schematic for Luxera’s Core bench board (the “brain” board that the glasses’ electronics get proven on before shrinking into the frame).

What’s in it:

• Full battery power chain: USB-C in → MCP73831 charger → 2 parallel Li-ion cells → MAX17048 fuel gauge
• Three regulated rails: 3.3V buck (TPS62840), 1.8V LDO, and a 5V boost (TPS61023) for the compute module
• Socket for the RK3566 compute module (CM4-compatible, 2× 100-pin DF40 connectors, ~60 pins wired: power, USB, I²C, UART console, boot control)
• Two MAX98357A I²S amps for bone-conduction audio (left + right channels via SD_MODE resistor trick)
• Capacitive touch controller (IQS227B) + multifunction button
• Camera (2-lane MIPI CSI) + display (2-lane DSI) lanes broken out, and a 40-pin FFC that will link to the sensor board in the glasses’ front frame

Hard-won lessons today:

• Learned the difference between buck and boost topology the practical way — the inductor goes before SW on a boost, not after 😅
• ERC threw 140+ “errors” that were all one thing: the LCSC import tool doesn’t set pin types. Learned to read the report instead of panicking — it actually became a free wiring audit
• Caught a real bug in review: my camera I²C clock label had landed on pin 90 (a 1.8V power output!) instead of pin 80. Hover-checking pins is now religion

Next: footprint assignment, then the actual PCB layout — 4-layer board, 55×45mm.

Every part verified in stock at JLCPCB/LCSC. Repo committed. 🔧