The Frame Finally Looks Like Glasses, and the Chip Became the Real Problem

Rough stretch, and an honest one. The frame went through a full rebuild from zero, and the thing blocking it turned out not to be CAD at all.

What broke, and why

The old front was built by offsetting the traced lens outline outward in steps. It kept producing wavy rims, voids, and in one build a front that was just a flat bar with the lens contour hanging below it as a free wire. No rim, no groove, nothing to hold a lens. I looked at the renders and told the tool it was garbage, because it was.

Worse, I found the artifacts on disk were 15 days older than the geometry file that generated them. The parameters had been fixed, the exports never ran. So every render and every STL I had been judging showed the version I had already rejected. I had never actually seen the fixed frame. Fix: a freshness gate that fails the build if any generated file is older than its source. That check now runs at the end of every geometry run.

The rebuild that worked

New method, closer to how real acetate frames are made: define one rim cross section, including the V groove that retains the lens, then sweep it along the traced lens contour. Uniform rim width and a working groove by construction, instead of hoping an offset chain behaves.

It worked first try. The front now reads as eyewear: continuous rim around both lenses, a real groove, an anatomical nose saddle, 44.86 mm tall. Side by side with my donor frame it is the same class of object.

What is still wrong

• The brow bar is a straight slab spanning the whole front and overhanging sideways. It needs to follow the lens tops like a real browline. Fix running now.
• The temples are a constant 21.4 mm tall for their whole length, where normal eyewear is 8 to 13 mm. Only the 40 mm section holding the main board needs that height. Per zone taper is running now.
• Worn weight is about 100 g against a 50 to 70 g target. Peers are 48 to 70 g.

The real finding

I kept asking why the temple could not get thinner, and the answer was the processor. The RK3566 is a 15.5 by 14.4 mm package, so the board cannot be narrower than about 16.3 mm, so the temple cannot be under about 19 mm. No layout change fixes that, because the chip itself is that wide.

Then it clicked: RK3566 is a tablet and set top box chip. It carries HDMI, gigabit Ethernet, SATA and multiple display controllers, none of which I use. I am paying package area for peripherals that do nothing in glasses. A wearable or camera class chip with similar cores, fewer peripherals, and memory stacked on top of the die instead of beside it can be far smaller at the same RAM. That stacking technique is how phones fit huge memory into no space.

So the hunt is on for a part that is Cortex A53 or A55 class, 512 MB or more of stacked or in package memory, under 12 mm, with camera, QSPI display, Wi Fi and audio interfaces.

The decision I changed my mind on

I was planning to keep the current chip for this revision and switch later. That is wrong. This revision exists to validate the platform, and if the next one changes the processor, all the bring up work, drivers and boot path get thrown away, and new silicon risk lands late in the hardest board. Both revisions have to run the same compute. So the chip study just became a blocking decision rather than a someday item.

Next

Finish the styling and thinning pass, get the chip answer with real datasheet numbers, and keep six vendor conversations moving on the display engine, the waveguide and the battery cells. Nothing ordered, no money spent yet.

The Frame Finally Looks Like Glasses, and the Chip Became the Real Problem

Rough stretch, and an honest one. The frame went through a full rebuild from zero, and the thing blocking it turned out not to be CAD at all.

What broke, and why

The old front was built by offsetting the traced lens outline outward in steps. It kept producing wavy rims, voids, and in one build a front that was just a flat bar with the lens contour hanging below it as a free wire. No rim, no groove, nothing to hold a lens. I looked at the renders and told the tool it was garbage, because it was.

Worse, I found the artifacts on disk were 15 days older than the geometry file that generated them. The parameters had been fixed, the exports never ran. So every render and every STL I had been judging showed the version I had already rejected. I had never actually seen the fixed frame. Fix: a freshness gate that fails the build if any generated file is older than its source. That check now runs at the end of every geometry run.

The rebuild that worked

New method, closer to how real acetate frames are made: define one rim cross section, including the V groove that retains the lens, then sweep it along the traced lens contour. Uniform rim width and a working groove by construction, instead of hoping an offset chain behaves.

It worked first try. The front now reads as eyewear: continuous rim around both lenses, a real groove, an anatomical nose saddle, 44.86 mm tall. Side by side with my donor frame it is the same class of object.

What is still wrong

• The brow bar is a straight slab spanning the whole front and overhanging sideways. It needs to follow the lens tops like a real browline. Fix running now.
• The temples are a constant 21.4 mm tall for their whole length, where normal eyewear is 8 to 13 mm. Only the 40 mm section holding the main board needs that height. Per zone taper is running now.
• Worn weight is about 100 g against a 50 to 70 g target. Peers are 48 to 70 g.

The real finding

I kept asking why the temple could not get thinner, and the answer was the processor. The RK3566 is a 15.5 by 14.4 mm package, so the board cannot be narrower than about 16.3 mm, so the temple cannot be under about 19 mm. No layout change fixes that, because the chip itself is that wide.

Then it clicked: RK3566 is a tablet and set top box chip. It carries HDMI, gigabit Ethernet, SATA and multiple display controllers, none of which I use. I am paying package area for peripherals that do nothing in glasses. A wearable or camera class chip with similar cores, fewer peripherals, and memory stacked on top of the die instead of beside it can be far smaller at the same RAM. That stacking technique is how phones fit huge memory into no space.

So the hunt is on for a part that is Cortex A53 or A55 class, 512 MB or more of stacked or in package memory, under 12 mm, with camera, QSPI display, Wi Fi and audio interfaces.

The decision I changed my mind on

I was planning to keep the current chip for this revision and switch later. That is wrong. This revision exists to validate the platform, and if the next one changes the processor, all the bring up work, drivers and boot path get thrown away, and new silicon risk lands late in the hardest board. Both revisions have to run the same compute. So the chip study just became a blocking decision rather than a someday item.

Next

Finish the styling and thinning pass, get the chip answer with real datasheet numbers, and keep six vendor conversations moving on the display engine, the waveguide and the battery cells. Nothing ordered, no money spent yet.

57.9 to 44.5 mm, Four Decisions Closed, and What Still Looks Wrong

Last log the frame was gray boxes. Now it is built around my own prescription lenses, the front dropped 13.4 mm, every open decision is closed, and some things still look bad.

The win

The front frame went from 57.9 mm tall to 44.46 mm. Derived, not guessed: my traced lens height (37.46 mm, confirmed against a 37 mm caliper reading) plus a 4.6 mm top rim and 2.4 mm bottom. Normal acetate frames run 40 to 45 mm, so the front is finally eyewear and not goggles. Apertures follow my actual lens contour, and the holes punched through the face are gone, replaced by camera and IR windows inside the corner blocks.

Decisions closed

Seating real parts in the real frame surfaced four issues. All resolved:

• Depth sensor aimed through my left lens. A prescription lens bends infrared, so readings would be garbage. Two placements now scored against real geometry, with a hard rule that it never fires through a lens.
• A connector clearance conflict gets fixed in the frame, not the board, because the frame is parametric code and the board waits on a paid review. Do not spend review money on what a frame tweak solves.
• A board height overrun goes to that review, with a new requirement: the reviewer returns a maximum component height so the pocket becomes a design rule, not a late surprise.
• Rigid versus rigid-flex. The sensor strip could not route on two layers, and two independent attempts hit the same wall. Decision: 4-layer rigid now, rigid-flex for production. Rigid-flex costs several times more per run and first revisions always respin, so prove it cheap, then convert.

What still looks wrong

Not pretending the renders are pretty:

• A void at the lower middle of the lens area, and the left aperture renders closed in some views, cut in others. Failed boolean, real breakage.
• The bone conduction driver sticks out behind the ear as a ball on a stick. Deleted unconditionally. Fix: move the driver forward into the temple zone over the temporal bone just in front of the ear, where the arm is already full thickness, so it vanishes. Fallback is a small downward firing open ear speaker, visible only as tiny ports underneath, which is what Ray-Ban Meta and Monako do.
• The nose bridge bulges forward as a tab. A real saddle scoops inward.
• Lens rims are wavy and the two openings differ more than my lenses do.

Root cause: code CAD is excellent at holes, pockets, walls and clearances, and bad at smooth flowing eyewear surfaces.

Tooling change

I connected Fusion 360 to Claude Code over an MCP bridge. An add-in runs inside Fusion and the agent gets two tools: execute Python with full API access, and screenshot the viewport. That second one matters most, because the tool can finally see its own work and catch a blob before I do. Code stays master for engineering geometry and verification, Fusion becomes master for the exterior surface, and they meet through STEP.

Other finds

• A possible Wi-Fi gap. The bench board got Wi-Fi free inside its compute module, but the in-frame board is a bare processor with no radio. Being audited, and if missing, the module goes into empty board area that already exists.
• Display vendor replied. They will support a small prototype order, but pricing sits behind an NDA and onboarding, so that is the optics bottleneck. Meanwhile I am opening two more waveguide vendors so no single supplier can hold this hostage. One mass produces a waveguide targeting fifty dollars against the hundreds I budgeted.

Images

1. front-old-vs-new.png: the 57.9 mm slab beside the 44.5 mm frame
2. front_frame-front.png: the new front, following my real lens contour
3. assembly-hook-closeup.png: the lollipop, the defect being deleted
4. assembly-iso.png: current assembly

Next: fix the four defects, sculpt in Fusion, print the right temple and wear it.

57.9 to 44.5 mm, Four Decisions Closed, and What Still Looks Wrong

Last log the frame was gray boxes. Now it is built around my own prescription lenses, the front dropped 13.4 mm, every open decision is closed, and some things still look bad.

The win

The front frame went from 57.9 mm tall to 44.46 mm. Derived, not guessed: my traced lens height (37.46 mm, confirmed against a 37 mm caliper reading) plus a 4.6 mm top rim and 2.4 mm bottom. Normal acetate frames run 40 to 45 mm, so the front is finally eyewear and not goggles. Apertures follow my actual lens contour, and the holes punched through the face are gone, replaced by camera and IR windows inside the corner blocks.

Decisions closed

Seating real parts in the real frame surfaced four issues. All resolved:

• Depth sensor aimed through my left lens. A prescription lens bends infrared, so readings would be garbage. Two placements now scored against real geometry, with a hard rule that it never fires through a lens.
• A connector clearance conflict gets fixed in the frame, not the board, because the frame is parametric code and the board waits on a paid review. Do not spend review money on what a frame tweak solves.
• A board height overrun goes to that review, with a new requirement: the reviewer returns a maximum component height so the pocket becomes a design rule, not a late surprise.
• Rigid versus rigid-flex. The sensor strip could not route on two layers, and two independent attempts hit the same wall. Decision: 4-layer rigid now, rigid-flex for production. Rigid-flex costs several times more per run and first revisions always respin, so prove it cheap, then convert.

What still looks wrong

Not pretending the renders are pretty:

• A void at the lower middle of the lens area, and the left aperture renders closed in some views, cut in others. Failed boolean, real breakage.
• The bone conduction driver sticks out behind the ear as a ball on a stick. Deleted unconditionally. Fix: move the driver forward into the temple zone over the temporal bone just in front of the ear, where the arm is already full thickness, so it vanishes. Fallback is a small downward firing open ear speaker, visible only as tiny ports underneath, which is what Ray-Ban Meta and Monako do.
• The nose bridge bulges forward as a tab. A real saddle scoops inward.
• Lens rims are wavy and the two openings differ more than my lenses do.

Root cause: code CAD is excellent at holes, pockets, walls and clearances, and bad at smooth flowing eyewear surfaces.

Tooling change

I connected Fusion 360 to Claude Code over an MCP bridge. An add-in runs inside Fusion and the agent gets two tools: execute Python with full API access, and screenshot the viewport. That second one matters most, because the tool can finally see its own work and catch a blob before I do. Code stays master for engineering geometry and verification, Fusion becomes master for the exterior surface, and they meet through STEP.

Other finds

• A possible Wi-Fi gap. The bench board got Wi-Fi free inside its compute module, but the in-frame board is a bare processor with no radio. Being audited, and if missing, the module goes into empty board area that already exists.
• Display vendor replied. They will support a small prototype order, but pricing sits behind an NDA and onboarding, so that is the optics bottleneck. Meanwhile I am opening two more waveguide vendors so no single supplier can hold this hostage. One mass produces a waveguide targeting fifty dollars against the hundreds I budgeted.

Images

1. front-old-vs-new.png: the 57.9 mm slab beside the 44.5 mm frame
2. front_frame-front.png: the new front, following my real lens contour
3. assembly-hook-closeup.png: the lollipop, the defect being deleted
4. assembly-iso.png: current assembly

Next: fix the four defects, sculpt in Fusion, print the right temple and wear it.

Six Boards Done, a Real Frame, and a Display Vendor Discovery

Big stretch since the last log: the program crossed from designing into spending mode, the frame became real CAD, and we found a vendor that might cut the biggest cost line in half.

What got done

• All six PCBs are fab-pack complete. Three bench boards (core, front, aux) and three in-frame prototype boards (p-core, p-front, p-aux), each with schematics, routed layout, gerbers, LCSC BOM, and pick and place files ready for JLCPCB. The hardest, p-core, carries a bare RK3566 with hand-routed LPDDR4 on 6-layer HDI.
• A full cost model with live pricing. One complete set of everything lands between $1,143 and $1,972, and the display engine alone is 44 to 51 percent of that.
• A 70-check verification pass: 50 clean, 15 documented exceptions, 5 real problems caught and fixed same day. Plus a 16-page Program Review PDF built from a script.
• Frame CAD v1, written as parametric code (build123d): seven printable pieces, split-half temples with a screwless post-in-socket board capture, my ear hook as one tangent chain, print-ready STL and STEP exports.

What we found

Verification is not paperwork, it keeps catching real things:

• The chirality catch. Seating the real p-core model in the real temple cavity showed the layout mirrored the wrong way, breaching the inner wall. The old box-based fit check could never see this. Caught before fab, so the fix is free.
• The 57.9 mm front. CAD proved the drawn 42 mm front cannot hold the old front board channel with legal walls. That forced a better architecture: camera flex straight to the main temple board (like shipped products), front board replaced by one thin sensor strip. Slimmer front, fewer connectors.
• Hongshi. A Chinese MicroLED maker building mono green microdisplays: 0.08 and 0.12 inch, 640x480, up to 8 million nits, SPI/QSPI native so zero changes to my boards, plus a matched engine + waveguide module that could collapse my two riskiest cost lines into one part. One of only two mass-production mono-green makers (the other is JBD). RFQ sent in English and Chinese.
• Samsung entered the category the same week: camera plus Gemini, no display, phone-tethered. Exactly the gap Luxera plays in: standalone Linux, an actual HUD, Arabic first.
• My prescription became a spec. I traced my real lenses (52□18-140, R.E. -2.00, L.E. -1.00, IPD 64.0) so the next frame is built around actual lens outlines. Bonus: the IPD is the display alignment target, since a monocular eyebox must center on the pupil, about 3 mm nasal of the lens center.

What is next

• The big rebuild: p-sense strip, p-core respin (mirror fix plus new connectors), and the frame regenerated around my real lens shapes with an anatomical nose bridge and hinge knuckles fused so every part prints as one watertight solid.
• MSLA print the right temple and wear-test the hook. Live JLCPCB quotes (quote only). Hongshi quote lands, then the engine decision vs JBD. Then the manager showcase.

The workflow, honestly

Claude Code is the engineering copilot: it writes the KiCad files and the CAD as code and runs for hours. I direct, review, catch the design smells, and make the calls. Nothing counts on vibes: every board answers to real ERC and DRC, every frame part to watertight, wall thickness, and collision checks. Longest single run: 2 days 15 hours.

Attached images

1. assembly-iso.png: frame CAD v1, full assembly
2. assembly-split-open.png: temples split open with the real boards seated inside
3. p-core-bottom.png: the prototype brain, bare RK3566 HDI board
4. p-front-iso.png: the front board that the new architecture retires

More soon: a printed temple, real quotes, and hopefully a display engine with a price tag.

Six Boards Done, a Real Frame, and a Display Vendor Discovery

Big stretch since the last log: the program crossed from designing into spending mode, the frame became real CAD, and we found a vendor that might cut the biggest cost line in half.

What got done

• All six PCBs are fab-pack complete. Three bench boards (core, front, aux) and three in-frame prototype boards (p-core, p-front, p-aux), each with schematics, routed layout, gerbers, LCSC BOM, and pick and place files ready for JLCPCB. The hardest, p-core, carries a bare RK3566 with hand-routed LPDDR4 on 6-layer HDI.
• A full cost model with live pricing. One complete set of everything lands between $1,143 and $1,972, and the display engine alone is 44 to 51 percent of that.
• A 70-check verification pass: 50 clean, 15 documented exceptions, 5 real problems caught and fixed same day. Plus a 16-page Program Review PDF built from a script.
• Frame CAD v1, written as parametric code (build123d): seven printable pieces, split-half temples with a screwless post-in-socket board capture, my ear hook as one tangent chain, print-ready STL and STEP exports.

What we found

Verification is not paperwork, it keeps catching real things:

• The chirality catch. Seating the real p-core model in the real temple cavity showed the layout mirrored the wrong way, breaching the inner wall. The old box-based fit check could never see this. Caught before fab, so the fix is free.
• The 57.9 mm front. CAD proved the drawn 42 mm front cannot hold the old front board channel with legal walls. That forced a better architecture: camera flex straight to the main temple board (like shipped products), front board replaced by one thin sensor strip. Slimmer front, fewer connectors.
• Hongshi. A Chinese MicroLED maker building mono green microdisplays: 0.08 and 0.12 inch, 640x480, up to 8 million nits, SPI/QSPI native so zero changes to my boards, plus a matched engine + waveguide module that could collapse my two riskiest cost lines into one part. One of only two mass-production mono-green makers (the other is JBD). RFQ sent in English and Chinese.
• Samsung entered the category the same week: camera plus Gemini, no display, phone-tethered. Exactly the gap Luxera plays in: standalone Linux, an actual HUD, Arabic first.
• My prescription became a spec. I traced my real lenses (52□18-140, R.E. -2.00, L.E. -1.00, IPD 64.0) so the next frame is built around actual lens outlines. Bonus: the IPD is the display alignment target, since a monocular eyebox must center on the pupil, about 3 mm nasal of the lens center.

What is next

• The big rebuild: p-sense strip, p-core respin (mirror fix plus new connectors), and the frame regenerated around my real lens shapes with an anatomical nose bridge and hinge knuckles fused so every part prints as one watertight solid.
• MSLA print the right temple and wear-test the hook. Live JLCPCB quotes (quote only). Hongshi quote lands, then the engine decision vs JBD. Then the manager showcase.

The workflow, honestly

Claude Code is the engineering copilot: it writes the KiCad files and the CAD as code and runs for hours. I direct, review, catch the design smells, and make the calls. Nothing counts on vibes: every board answers to real ERC and DRC, every frame part to watertight, wall thickness, and collision checks. Longest single run: 2 days 15 hours.

Attached images

1. assembly-iso.png: frame CAD v1, full assembly
2. assembly-split-open.png: temples split open with the real boards seated inside
3. p-core-bottom.png: the prototype brain, bare RK3566 HDI board
4. p-front-iso.png: the front board that the new architecture retires

More soon: a printed temple, real quotes, and hopefully a display engine with a price tag.

All 3 bench boards DONE (DRC zero) + a compute plot twist 🤯

Since last devlog the project went from “one schematic” to the entire bench board set finished and fab-ready — and one massive architecture correction.

Bench set — done ✅

• Core board routed from 149 unrouted nets → DRC ZERO (0 unconnected, 0 violations). Full JLCPCB fab pack: gerbers, BOM with LCSC part numbers, pick-and-place, assembly drawing.
• Front board (the 75mm rim board): camera FFC + VL53L8CX ToF + 2 PDM mics + voice-pickup sensor. Schematic ERC 0 → routed DRC 0 → fab pack.
• Aux board: nRF52832 BLE + BMI270/BMM150 IMU + bone-conduction audio. Same treatment, same result.

The routing war ⚔️

My custom A* autorouter got each board ~90% routed then hit a wall for days — escape congestion on 0.4mm-pitch connectors that greedy routing can’t solve. Fix: a fully headless pipeline —

KiCad Python API → Specctra DSN → Freerouting (real rip-up-and-reroute) → session import → kicad-cli DRC as the referee

The CSI fanout that blocked me for days fell in 28 seconds. Humbling.

The plot twist 🤯

The plan was a Radxa Zero 3W as the in-frame compute. Deep-dive before committing: it’s HDMI-only. No MIPI-DSI, no QSPI — it physically cannot drive the MicroLED display that the entire product exists for. Also it’s a 65×30mm brick that would never fit a glasses temple.

Killed it. Re-read the build guide cover to cover — the real design was always the bare RK3566 SoC soldered directly onto the temple board, with 2× LPDDR4 + eMMC + Rockchip’s RK817 PMIC around it.

So the real in-frame boards are now underway:

• Built the 565-ball, 0.4mm-pitch RK3566 BGA library part + LPDDR4 + eMMC + RK817 footprints — every ball count and pitch hand-verified against datasheets
• All three in-frame schematics at ERC 0 — the compute board alone is 171 parts, 508 nets, 1,396 pin connections wiring the bare SoC to everything
• Display path confirmed: RK3566 QSPI → JBD 0.13” green MicroLED engine — that’s how Vuzix/Rokid actually drive these engines, not DSI

Hard-won lessons 🔥

• Check the display bus before falling in love with a compute module. “Right SoC” ≠ “the pins you need are exposed.”
• Don’t rebuild mature tools: 8 sessions tuning a custom router lost to one afternoon of wiring Freerouting in headlessly.
• kicad-cli DRC re-reports exclusions the GUI accepts — document every waiver or your CI numbers lie.
• Imported BGA footprints are guilty until proven innocent — the PMIC footprint shipped with paste over its thermal vias (solder-wicking defect) and had to be reworked.

Next: layout + routing of the in-frame boards. The compute board is 6-layer HDI with DDR length-matching — that one gets a professional design review before any fab money. Then fab packs and the full branded bring-up & testing guide. 🔧

All 3 bench boards DONE (DRC zero) + a compute plot twist 🤯

Since last devlog the project went from “one schematic” to the entire bench board set finished and fab-ready — and one massive architecture correction.

Bench set — done ✅

• Core board routed from 149 unrouted nets → DRC ZERO (0 unconnected, 0 violations). Full JLCPCB fab pack: gerbers, BOM with LCSC part numbers, pick-and-place, assembly drawing.
• Front board (the 75mm rim board): camera FFC + VL53L8CX ToF + 2 PDM mics + voice-pickup sensor. Schematic ERC 0 → routed DRC 0 → fab pack.
• Aux board: nRF52832 BLE + BMI270/BMM150 IMU + bone-conduction audio. Same treatment, same result.

The routing war ⚔️

My custom A* autorouter got each board ~90% routed then hit a wall for days — escape congestion on 0.4mm-pitch connectors that greedy routing can’t solve. Fix: a fully headless pipeline —

KiCad Python API → Specctra DSN → Freerouting (real rip-up-and-reroute) → session import → kicad-cli DRC as the referee

The CSI fanout that blocked me for days fell in 28 seconds. Humbling.

The plot twist 🤯

The plan was a Radxa Zero 3W as the in-frame compute. Deep-dive before committing: it’s HDMI-only. No MIPI-DSI, no QSPI — it physically cannot drive the MicroLED display that the entire product exists for. Also it’s a 65×30mm brick that would never fit a glasses temple.

Killed it. Re-read the build guide cover to cover — the real design was always the bare RK3566 SoC soldered directly onto the temple board, with 2× LPDDR4 + eMMC + Rockchip’s RK817 PMIC around it.

So the real in-frame boards are now underway:

• Built the 565-ball, 0.4mm-pitch RK3566 BGA library part + LPDDR4 + eMMC + RK817 footprints — every ball count and pitch hand-verified against datasheets
• All three in-frame schematics at ERC 0 — the compute board alone is 171 parts, 508 nets, 1,396 pin connections wiring the bare SoC to everything
• Display path confirmed: RK3566 QSPI → JBD 0.13” green MicroLED engine — that’s how Vuzix/Rokid actually drive these engines, not DSI

Hard-won lessons 🔥

• Check the display bus before falling in love with a compute module. “Right SoC” ≠ “the pins you need are exposed.”
• Don’t rebuild mature tools: 8 sessions tuning a custom router lost to one afternoon of wiring Freerouting in headlessly.
• kicad-cli DRC re-reports exclusions the GUI accepts — document every waiver or your CI numbers lie.
• Imported BGA footprints are guilty until proven innocent — the PMIC footprint shipped with paste over its thermal vias (solder-wicking defect) and had to be reworked.

Next: layout + routing of the in-frame boards. The compute board is 6-layer HDI with DDR length-matching — that one gets a professional design review before any fab money. Then fab packs and the full branded bring-up & testing guide. 🔧

Core board schematic — DONE ✅

Finished the complete KiCad schematic for Luxera’s Core bench board (the “brain” board that the glasses’ electronics get proven on before shrinking into the frame).

What’s in it:

• Full battery power chain: USB-C in → MCP73831 charger → 2 parallel Li-ion cells → MAX17048 fuel gauge
• Three regulated rails: 3.3V buck (TPS62840), 1.8V LDO, and a 5V boost (TPS61023) for the compute module
• Socket for the RK3566 compute module (CM4-compatible, 2× 100-pin DF40 connectors, ~60 pins wired: power, USB, I²C, UART console, boot control)
• Two MAX98357A I²S amps for bone-conduction audio (left + right channels via SD_MODE resistor trick)
• Capacitive touch controller (IQS227B) + multifunction button
• Camera (2-lane MIPI CSI) + display (2-lane DSI) lanes broken out, and a 40-pin FFC that will link to the sensor board in the glasses’ front frame

Hard-won lessons today:

• Learned the difference between buck and boost topology the practical way — the inductor goes before SW on a boost, not after 😅
• ERC threw 140+ “errors” that were all one thing: the LCSC import tool doesn’t set pin types. Learned to read the report instead of panicking — it actually became a free wiring audit
• Caught a real bug in review: my camera I²C clock label had landed on pin 90 (a 1.8V power output!) instead of pin 80. Hover-checking pins is now religion

Next: footprint assignment, then the actual PCB layout — 4-layer board, 55×45mm.

Every part verified in stock at JLCPCB/LCSC. Repo committed. 🔧

Core board schematic — DONE ✅

Finished the complete KiCad schematic for Luxera’s Core bench board (the “brain” board that the glasses’ electronics get proven on before shrinking into the frame).

What’s in it:

• Full battery power chain: USB-C in → MCP73831 charger → 2 parallel Li-ion cells → MAX17048 fuel gauge
• Three regulated rails: 3.3V buck (TPS62840), 1.8V LDO, and a 5V boost (TPS61023) for the compute module
• Socket for the RK3566 compute module (CM4-compatible, 2× 100-pin DF40 connectors, ~60 pins wired: power, USB, I²C, UART console, boot control)
• Two MAX98357A I²S amps for bone-conduction audio (left + right channels via SD_MODE resistor trick)
• Capacitive touch controller (IQS227B) + multifunction button
• Camera (2-lane MIPI CSI) + display (2-lane DSI) lanes broken out, and a 40-pin FFC that will link to the sensor board in the glasses’ front frame

Hard-won lessons today:

• Learned the difference between buck and boost topology the practical way — the inductor goes before SW on a boost, not after 😅
• ERC threw 140+ “errors” that were all one thing: the LCSC import tool doesn’t set pin types. Learned to read the report instead of panicking — it actually became a free wiring audit
• Caught a real bug in review: my camera I²C clock label had landed on pin 90 (a 1.8V power output!) instead of pin 80. Hover-checking pins is now religion

Next: footprint assignment, then the actual PCB layout — 4-layer board, 55×45mm.

Every part verified in stock at JLCPCB/LCSC. Repo committed. 🔧