x86 based verilog simulation for exploring old 16 and 32 bit architecutre, with complete northbridge, southbridge, ide, pci and old hardware like the 3dfx/ati/nvidia cards and sound blaster emulation. Written in verilog.
Been working on this monstrosity of a motherboard for the 8088, still somehow not done lol (send help)
Gonna have to pivot to software, funding for hardware is hard frankly with all the backlog the reviewers have, so this will stick to strictly verilog simulation until I get the funding for building this myself. For now, I’ve only written the address decoder.
Next comes the fake ram simulation of a sdram, complete with chip select, bank select, row address strobe and column address strobe, bank precharge, data mask, along with row cycle time (tRC), RAS to CAS delay (tRCD), precharge command period (tRP), boot rom etc. We’ll see how stuff goes.
What is this? What am I making?
The Grip is an open-source x86-32 motherboard project built around a real AMD Am486DX4 or Am5x86 processor and an FPGA-based chipset.
The project will begin as a modular prototype using separate CPU, FPGA/memory, display, storage, audio, and controller boards connected through a backplane (read: jank setup of breadboard). Once the architecture is proven, these modules will be integrated into a final laptop motherboard and a 3d printed custom case.
The FPGA will replace the traditional northbridge and southbridge logic. It will handle CPU bus transactions, memory control, BIOS mapping, interrupts, timers, DMA, ISA, storage, display blah blah blah.
The planned final system includes 128 MB or more of SDRAM, SD based storage (no compactflash thank you), VGA graphics, LCD output, mouse/keeb support on PS/2, audio, floppy. OS Support will be first FreeDOS, then Linux Win95 and Win98.
The first major milestone is simple: release the processor from reset, detect its request for the reset vector, return valid instruction bytes, and complete the bus cycle. Simple, but if it works, we build on top of it.
spent roughly eight hours researching the 486 bus, drawing a timing diagram, and implementing the first version of the CPU bus frontend.
allat to send 4 x86 NOP instructions. crazy? i was crazy once.
(well i am still now)
Works simulated, lets see how it works with a proper full fledged simulated i486. i’ll borrow one from github to see if this works.
