Gonna have to pivot to software, funding for hardware is hard frankly with all the backlog the reviewers have, so this will stick to strictly verilog simulation until I get the funding for building this myself. For now, I’ve only written the address decoder.

Next comes the fake ram simulation of a sdram, complete with chip select, bank select, row address strobe and column address strobe, bank precharge, data mask, along with row cycle time (tRC), RAS to CAS delay (tRCD), precharge command period (tRP), boot rom etc. We’ll see how stuff goes.