@12zcab

HELLO ITS Day two of my proj
i realized im a bit over-affected by Z80
If i continue this thing the whole thing resulted will be a weird thing remapped from Z80 IS Table BRUHHHH
so imma work on a more simple mechanic.
the whole thing will be mainly 2 instruction types:
Load:
Including
LD 8REG,8REG LD 8REG,n LD 8REG,[HL] LD [HL],8REG
LD 16REG,16REG LD 16REG,nn
PUSH 16REG
POP 16REG
CALL
RETURN
JUMP

Calculate:
Including ADD SUB ADC SBC AND XOR OR Compare Bitwise Edit INC DEC

But why? why i decided to treat CALL RETURN JUMP as Load?
its because those Instructions are actually PUSH PC LD PC,nn POP PC and LD PC,nn :|

and for ADD and SUB I only need to set Carry Input as 1 and Port B Input Inverted.
and for ADC and SBC its actually a ADD with Carry Input and a ADD with Inverted Carry Input.

so its actually something like this:
=====|ADD|SUB|ADC|SBC|
PortA|A__|A__|A__|A__|
PortB|B__|~B_|||
In_C_|0__|1__|C__|~C_| <- and its actually XOR(x,AND(y,C))

the Final ALU will actually be two parts 1:ADD 2:Logic

erm so about the Compare thing its just SUB with Flag Register Input Disabled
then the Bitwise Edit i think i will not handle it right now cuz they can be easily programed with logic in assembly programming.
for the INC and DEC i just simply need to add a switching gate to select Port B as INC and DEC

Also i wanna try to open Register F as a Editable Register
it will be updated by ALU but also allowed to be edited by human

so i think its kinda enough right now..?

so we will hv
Reg8 list of B C D E H L A F
Reg16 list of BC DE HL AF SP PC Immediate
Special 8 bit of [HL],Immediate
the normal Load for 8 bit:
00[reg1][reg2]

the normal for 16 bit:
01[reg16 1][reg16 2]

the special 8 bit will be mapped later
then 10[x][y][reg1] will be for |ADD|SUB|ADC|SBC|

hummm looks nice may be this is enough for today

Yup
So now its 30/7/2026 U+8 Timezone 17:44 in HK rn
and lets start a new project to make a 8 bit Computer!
so the most important thing right now is to design the CPU that runs my own IS!

so i want the IS to be 1 Byte mainly and similar to z80 i think
may be 8 registers in total
(i REALLY LIKE Z80’s Design)
so im gonna use may be something like
AF (67)
BC (01)
DE (23)
HL (45)

with
PC
SP
as special register

so i need instructions like:
Load Reg,Reg
Args: 3Bit 8Reg x2

Load Reg,IMME
Args: 3Bit 8Reg and 8 Bit Value

Load Reg,[HL]
Args: 3Bit 8Reg

Load [HL],Reg
Args: 3Bit 8Reg

Load 16Reg,16Reg
Args: 3Bit 16Reg x2

Load 16Reg,IMME
Args: 3Bit 16Reg and 16 Bit Value]

Load [IMME],A
Args: 16 Bit Address

Load A,[IMME]
Args: 16 Bit Address

i think this will be enough for Load?

so actually we can group the commands to make it easier for Logic Circuit to identify them

such as Load Reg,[HL] and Load [HL],Reg actually have a really similar structure with only the direction difference so we can organize into a thing like
?Bit [Special LD] 1Bit [Direction(0=Reg->HL 1=HL->Reg)] 3Bit [Register]

also REG7 (REG F) actually not really useful for LD Instruction so we can make it [HL] Symbol
like LDPREFIX 000,111 means Load a Addressed Value to REG B

ok so it will hv something like
[8Bit LD Prefix] [REG1] [REG2]
for
Load Reg,Reg
Load Reg,[HL]
Load [HL],Reg

also Load [HL],[HL] is impossible cuz u need to Fetch and Write Back to memory in the same Instruction Cycle so we can let it be HALT (Just like how engineers did when design z80 LOL)

erm yah i think thats all for today :|