RISC-V Emulator
- 1 Devlogs
- 7 Total hours
A bare-metal, 32-bit RISC-V CPU emulator written entirely in Rust as a learning project.
Ship #1
Pending review
@jayanth_raveendra
on
RISC-V Emulator
A bare-metal, 32-bit RISC-V CPU emulator written entirely in Rust from scratch. It features a simulated 1MB memory array, a full RV32I base integer decoding pipeline, and Memory-Mapped I/O (MMIO) that intercepts writes to a specific memory address to simulate a physical terminal screen.
Instead of just running standard assembly, I built a proxy-kernel into the emulator to intercept RISC-V ecall instructions (Syscall 64 for write and Syscall 93 for exit). Alongside a custom Makefile and linker script setup, this allows the emulator to natively execute freestanding, bare-metal C programs compiled via a Linux RISC-V cross-compiler toolchain.
@jayanth_raveendra
on
RISC-V Emulator
6h 56m 8s logged
Spent the almost 7 hours building a bare-metal, 32-bit RISC-V CPU emulator entirely in Rust from scratch! I finished the core RV32I instruction decoding and set up a simulated 1MB memory array, but getting actual C code to run on it was a massive challenge. I ran into two brutal bugs: The GCC cross-compiler was secretly compressing my instructions into 16-bit chunks, causing my 32-bit fetch() cycle to mash instructions together into unknown opcodes. I had to configure -march=rv32i to force strict 32-bit mode. My CPU tried to jump to an address 4.2 billion bytes out of bounds because of a 64-bit sign-extension trap in Rust! After fixing those, I wrote a tiny bootloader routine to set the Stack Pointer (x2), built a proxy-kernel to handle ecall system traps, and set up Memory-Mapped I/O (MMIO). The emulator can now successfully run a freestanding C program, print to a fake terminal screen, and exit cleanly!
