Finally the errors disappeared… it turns out you had the custom DRC rules that I set. Then, like 2 or 3 NETs had thickness rules that couldn’t be followed because QFN components and the VSON package type have pads really close to each other (pitch), so there was no way to route 0.8mm traces on components with, like, 0.4mm pitch. Obviously, you had to reduce it to make it work, but I didn’t know by how much and whether it might be wrong at some point, cause problems, or lower the PCB’s lifespan. 😶

I figured out how to change the rules and get things fixed and done. Man, I think I should review it again and really check some automatic NETs from the editor. After all these days without touching this, I noticed there were these NETs without descriptive names. I don’t remember if it’s because I didn’t assign a NET, or if it’s just that connection between those pins or something like that. But overall it’s going to be easy.

I really hope SO MUCH!

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