SystemVerilog Update

I haven’t had too much time to work on my project lately, but I have some updates:

1. SystemVerilog is officially done! The project, at it’s current state (I got a lot of stuff planned to add later) is officially done! The CPU is Turing Complete, and can do all of your basic operations, read/write to/from memory, and even has a BIOS mode that redirects memory reads to ROM to load an actual BIOS! This means I can program an OS to be loaded by the BIOS!
2. Inputs and Outputs can now be provided to the CPU by the user! Previously, if you wanted to, for example, see the output of an instruction or provide dynamic data to the CPU, you would have to rewrite the ENTIRE program and hardcode those details into it. Now, with the new UART transciever that runs at a measly Baud Rate of 9600, things like ASCII characters can be both send or recieved to/from the CPU!
3. A bunch of minor upgrades, such as (but not limited to): MMIO (no uses as of right now, but the wiring exists in the CPU), CPU stalls (so that you don’t accidentally read memory that hasn’t been written), an entire interrupt system (with a hardware timer interrupt!), etc.

Things I have planned:

1. A Standard Library (as of right now, still on paper :(. Making a list of modules and functions)
2. More MMIO uses (a display output!)
3. VGA drivers (part of the goal for a display output)
4. Emulator Update (for UART experiments)
5. USB drivers? (zero progress currently, but maybe a far-off goal; UART is good enough for now)