SSE register state switching!

The kernel will now switch the SSE register state lazily, but I still have two problems:

• The Part for the registers in the TCB must be 16 byte aligned, which it currently not guaranteed
• The interrupt handlers are not allowed to use SSE instructions, but I have no way of verifying this

Road map

I think it is time to write a version of malloc() which can guarantee a specified alignment. After that, I can try to actually switch tasks automatically with a simple scheduler! I will probably use the PIT interrupt to switch to the next task in a list.