SSE support

SSE is an extension of the CPU which has 16 128-bit registers, but is rarely used. This means, that saving all of these registers every time a task switch occurs would cost some performance. For this reason, the CPU has a bit that can be set to indicate that a task switch occurred. In most cases, nothing happens and the registers are kept in their original state. But if a task needs to use SSE instructions, the CPU generates an interrupt, which manually saves the SSE registers. This is what I am working on currently.

Custom ISR wrapper

All interrupt handlers use now my custom wrappers, which made possible that I can work on SSE support.