I/O APIC

As I explained earlier, I need to configure the APIC to get interrupts. I think I only need the I/O APIC and not the local APIC, if I understand the limine documentation correctly. But when trying to access it’s registers, I got a page fault. It seems like I need to manually map the registers to virtual memory, which brings me to…

Physical Memory Manager

I need to do what I already feared when starting to write the PMM, manually editing page tables. I am working on a function which will map pages (Including the I/O APIC registers) to virtual addresses. For this, I need to walk the complete paging structure:
PML4 (from cr3) -> PDPT -> PD -> PT
I can already parse it until I have the PT’s address, but when accessing the PT I get a page fault, as you can see on the screenshot.

Road map

I just wanted to post this update so that the next devlog is not too long. I will continue to work on the PMM, until I can access the I/O APIC’s registers.