Clock & fixes

Clock

Basically the typical Ben Eater’s design of the clock module, nothing special, uses 3 555 timers in different configurations for both the manual step and the actual clock.

Flags register

Now the flags register has 4 flags, Negative, Carry, Zero and oVerflow. N flag is generated using the MSB of the sum out, since that would indicate a negative number when doing signed arithmetic. Zero is generated by ORing all the sum out and ANDing them together. The Carry flag is just taken directly from the 181 ALU. The Overflow flag comes from by NOT(XOR A7, B7) AND XOR(S7, A7)

Fixes

Now the load control words for registers are synchronous, this prevents issues with loading garbage from the bus close to clock transitions. Another fix was that the CF reader missed a VCC pin so I added that back.