MAR, PC, SP

Made the schematic for the memory address register, program counter and the stack pointer.
All 3 modules output to a shared 16bit memory address bus.
Since the bus is 8 bit and the address bus is 16bit, the MAR, PC, and the SP are split into a High and a Low section, so it takes 2 fetch cycles to load a 16bit address into the modules (ie first fetch loads 8 bit into MAR_Low and second fetch loads 8 bit into MAR_High).

MAR

The MAR uses 2 74LS573 octal d-type registers to store 16 bits of information, it’s used for instructions needing to access data in RAM, ie LDA 0x7000. To allow for viewing the MAR data, its hooked up to LEDs and to the address bus using 2 74LS245 to act as buffer between the MAR and the address bus.

PC

The program counter uses 4 74LS161 to count up. I considered using the 74LS593, but after a quick search on Aliexpress and LCSC, found it too rare of a chip to use. So I went back to using the 74LS161. The program counter tells the computer what is the next memory address to fetch data from. This module is also hooked up to the main data bus to allow for jump instructions to work. This is also buffered via 2 74LS245.

SP

The stack pointer uses 4 74LS193 to allow for it to count up and down. First time using the 74LS193 so it was kinda confusing to figure out how to wire multiple of them up for cascading. The SP allows for subroutines to happen (JSR/CALL/RTS/RET instructions) as it allows for the computer to remember where to return to after the subroutine finishes. This is also buffered via 2 74LS245.