Devlog #4
Finished assigning the footprints for the project and finally got a completely clean ERC with 0 errors.
Moved into the PCB editor after that and immediately hit the 100x100mm size constraint. My first layout came in at 108mm vertically, so I spent a while compressing the diagonal switch stagger, tightening spacing to exactly 19.05mm, and moving the OLED header and capacitor out of dead space.
Then I tried to reclaim even more space by tucking the XIAO underneath three of the switches instead of placing it separately, since it’s flipped to the back layer anyway for assembly. Ran DRC to check for collisions and it came back ugly, with actual solder mask bridges between XIAO pins and switch pins on completely different nets. Also had courtyard overlaps between a few diodes and switches, and hadn’t drawn the board outline yet so some checks couldn’t even run properly.

Challenges:
I’m still learning that even parts on opposite layers can collide, as the pins themselves are still physical holes drilled through the entire board. So a switch’s hole and the XIAO’s pad can still land on top of each other even though the components sit on opposite faces.

Next Steps:
I’m going to scrap the XIAO-under-switches idea. Going back to a layout where nothing overlaps, and instead squeezing space by tightening gaps between all components more aggressively across the whole board. Once placement is solid and collision-free, I can finally draw the board outline and start routing.